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| Freescale Semiconductor, Inc. HC05E5GRS/D REV. 1.0 Freescale Semiconductor, Inc... General Release Specification CSIC MCU Design Center Austin, Texas For More Information On This Product, Go to: www.freescale.com NON-DISCLOSURE February 3, 1997 AGREEMENT MC68HC05E5 REQUIRED Freescale Semiconductor, Inc. General Release Specifiation REQUIRED NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 List of Sections Section 1. General Description . . . . . . . . . . . . . . . . . . . 15 Freescale Semiconductor, Inc... Section 2. Memory . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Section 3. Central Processing Unit (CPU) . . . . . . . . . . . 27 Section 4. Interrupts . . . . . . . . . . . . . . . . . . . . . . . . . . . . 31 Section 5. Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Section 6. Operating Modes . . . . . . . . . . . . . . . . . . . . . 45 Section 7. Input/Output (I/O) Ports . . . . . . . . . . . . . . . . 49 Section 8. Timer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53 Section 9. Phase-Locked Loop (PLL) Synthesis . . . . . . 59 Section 10. Computer Operating Properly (COP) Watchdog . . . . . . . . . . 65 Section 11. Motorola Bus (M Bus) Interface . . . . . . . . . 69 Section 12. Synchronous Serial Interface (SSI) . . . . . . 93 Section 13. Instruction Set . . . . . . . . . . . . . . . . . . . . . . 105 Section 14. Electrical Specifications . . . . . . . . . . . . . . 123 Section 15. Mechanical Data . . . . . . . . . . . . . . . . . . . 133 Section 16. Ordering Information . . . . . . . . . . . . . . . . 135 MC68HC05E5 -- Rev. 1.0 List of Sections For More Information On This Product, Go to: www.freescale.com General Release Specification NONDISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. List of Sections REQUIRED NONDISCLOSURE General Release Specification List of Sections For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Table of Contents Section 1. General Description 1.1 1.2 1.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Freescale Semiconductor, Inc... 1.4 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.2 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.3 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.5 PA0-PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.6 PB0-PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.7 PC0-PC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.8 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.9 VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 Section 2. Memory 2.1 2.2 2.3 2.4 2.5 2.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Section 3. Central Processing Unit (CPU) 3.1 3.2 3.3 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 MC68HC05E5 -- Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification NONDISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Table of Contents REQUIRED 3.4 3.5 3.6 3.7 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Section 4. Interrupts 4.1 4.2 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .33 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Custom Periodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . . . .37 Synchronous Serial Interface Interrupt (SSI) . . . . . . . . . . . . . .38 M-Bus (I2C) Interrupt (M Bus). . . . . . . . . . . . . . . . . . . . . . . . . .38 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .38 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .38 Freescale Semiconductor, Inc... AGREEMENT Section 5. Resets 5.1 5.2 5.3 5.4 5.5 5.6 5.6.1 5.6.2 5.6.3 5.6.4 5.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Computer Operating Properly Reset (COPR). . . . . . . . . . . . . .43 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 COP During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .43 COP During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .43 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . .44 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 NONDISCLOSURE Section 6. Operating Modes 6.1 6.2 General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Table of Contents Section 7. Input/Output (I/O) Ports Freescale Semiconductor, Inc... Section 8. Timer 8.1 8.2 8.3 8.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Timer Control and Status Register . . . . . . . . . . . . . . . . . . . . . .55 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 9.1 9.2 9.3 9.4 9.5 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .61 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .63 Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Section 10. Computer Operating Properly (COP) Watchdog 10.1 10.2 10.3 10.4 10.5 MC68HC05E5 -- Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 System Control and Status Register. . . . . . . . . . . . . . . . . . . . .66 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 General Release Specification NONDISCLOSURE Section 9. Phase-Locked Loop (PLL) Synthesis AGREEMENT 7.1 7.2 7.3 7.4 7.5 7.6 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 REQUIRED 6.3 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.4 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.5.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.5.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.5.3 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 11. Motorola Bus (M Bus) Interface 11.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .69 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 11.3 M-Bus Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 11.4 M-Bus System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .71 11.5 M-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 11.5.1 Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 11.5.2 Slave Address Transmission. . . . . . . . . . . . . . . . . . . . . . . .73 11.5.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.5.4 Repeated Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11.5.5 Stop Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11.5.6 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11.5.7 Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 11.5.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 11.6 M-Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.6.1 M-Bus Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.6.2 M-Bus Frequency Divider Register . . . . . . . . . . . . . . . . . . .78 11.6.3 M-Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 11.6.4 M-Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 11.6.5 M-Bus Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . .84 11.7 M-Bus Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.8 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.8.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.8.2 Generation of a Start Signal and the First Byte of Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .87 11.8.3 Software Responses after Transmission or Reception of a Byte . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.8.4 Generation of the Stop Signal . . . . . . . . . . . . . . . . . . . . . . .89 11.8.5 Generation of a Repeated Start Signal . . . . . . . . . . . . . . . .90 11.8.6 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.8.7 Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 11.9 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.10 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91 NONDISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Table of Contents Freescale Semiconductor, Inc... Section 13. Instruction Set 13.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .105 13.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 13.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 13.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 13.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 13.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 13.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 13.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 13.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 13.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .110 13.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .111 13.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .112 13.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .114 13.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 13.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 MC68HC05E5 -- Rev. 1.0 Table of Contents For More Information On This Product, Go to: www.freescale.com General Release Specification NONDISCLOSURE AGREEMENT 12.1 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .93 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 12.3 SSI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.2 Serial Data Input/Output (SDIO) . . . . . . . . . . . . . . . . . . . . .96 12.4 SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.4.1 SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.4.2 SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.4.3 SSI Data Register (SDR). . . . . . . . . . . . . . . . . . . . . . . . . .102 12.5 SSI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 12.6 SSI During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 12.7 SSI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 REQUIRED Section 12. Synchronous Serial Interface (SSI) Freescale Semiconductor, Inc. Table of Contents REQUIRED Section 14. Electrical Specifications 14.1 14.2 14.3 14.4 14.5 14.6 14.7 14.8 14.9 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .125 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .126 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 M-Bus Interface Input Signal Timing. . . . . . . . . . . . . . . . . . . .130 M-Bus Interface Output Signal Timing . . . . . . . . . . . . . . . . . .130 Freescale Semiconductor, Inc... AGREEMENT Section 15. Mechanical Data 15.1 15.2 15.3 15.4 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 28-Pin Plastic Dual-in-Line Package (Case 710-02) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .134 Section 16. Ordering Information 16.1 16.2 16.3 16.4 16.5 16.6 16.7 Contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .136 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .137 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .138 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 NONDISCLOSURE General Release Specification Table of Contents For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 List of Figures Figure Title Page Freescale Semiconductor, Inc... 2-1 2-2 3-1 3-2 3-3 3-4 3-5 3-6 3-7 4-1 4-2 4-3 Memory Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 I/O Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Programming Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Stacking Order . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Accumulator (A) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Index Register (X) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Condition Code Register (CCR) . . . . . . . . . . . . . . . . . . . . . .29 Stack Pointer (SP) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Program Counter (PC) . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Interrupt Processing Flowchart. . . . . . . . . . . . . . . . . . . . . . .35 STOP/WAIT Flowcharts . . . . . . . . . . . . . . . . . . . . . . . . . . . .36 Custom Periodic Interrupt Control and Status Register (CPICSR) . . . . . . . . . . . . . . . . . . . .37 Reset Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 RESET and POR Timing Diagram . . . . . . . . . . . . . . . . . . . .41 Port I/O Circuitry. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 Timer Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .54 Timer Control and Status Register (TCSR) . . . . . . . . . . . . .55 Timer Counter Register (TCR) . . . . . . . . . . . . . . . . . . . . . . .57 5-1 5-2 7-1 8-1 8-2 8-3 MC68HC05E5 -- Rev. 1.0 List of Figures For More Information On This Product, Go to: www.freescale.com General Release Specification NONDISCLOSURE AGREEMENT 1-1 1-2 1-3 Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .17 Single-Chip Mode Pinout . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Oscillator Connections . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 REQUIRED Freescale Semiconductor, Inc. List of Figures REQUIRED Figure 9-1 9-2 10-1 11-1 11-2 11-3 11-4 11-5 11-6 11-7 11-8 11-9 12-1 12-2 12-3 12-4 12-5 12-6 14-1 14-2 14-3 14-4 14-5 Title Page PLL Circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .60 Phase-Locked Loop Control Register (PLLCR) . . . . . . . . . .61 System Control and Status Register (SCSR) . . . . . . . . . . . .66 M-Bus Transmission Signal Diagram . . . . . . . . . . . . . . . . . .72 Clock Synchronization . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 M-Bus Address Register (MADR) . . . . . . . . . . . . . . . . . . . .76 M-Bus Interface Block Diagram . . . . . . . . . . . . . . . . . . . . . .77 M-Bus Frequency Divider Register (MFDR). . . . . . . . . . . . .78 M-Bus Control Register (MCR) . . . . . . . . . . . . . . . . . . . . . .80 M-Bus Status Register (MSR) . . . . . . . . . . . . . . . . . . . . . . .82 M-Bus Data I/O Register (MDR). . . . . . . . . . . . . . . . . . . . . .84 Flowchart of M-Bus Interrupt Routine. . . . . . . . . . . . . . . . . .85 SSI Block Diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .95 Synchronous Serial Interface Timing (CPOL = 1) . . . . . . . .97 Synchronous Serial Interface Timing (CPOL = 0) . . . . . . . .97 SSI Control Register (SCR) . . . . . . . . . . . . . . . . . . . . . . . . .98 SSI Status Register (SSR) . . . . . . . . . . . . . . . . . . . . . . . . .101 SSI Data Register (SDR) . . . . . . . . . . . . . . . . . . . . . . . . . .102 Maximum Supply Current versus Operating Frequency . .127 Typical Supply Current versus Operating Frequency. . . . .127 External Interrupt Mode Diagram . . . . . . . . . . . . . . . . . . . .128 Power-On Reset and RESET. . . . . . . . . . . . . . . . . . . . . . .129 M-Bus Interface Timing . . . . . . . . . . . . . . . . . . . . . . . . . . .131 NONDISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification List of Figures For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 List of Tables Table Title Page Freescale Semiconductor, Inc... 4-1 5-1 6-1 7-1 8-1 9-1 10-1 11-1 12-1 13-1 13-2 13-3 13-4 13-5 13-6 13-7 16-1 Vector Address for Interrupts and Reset . . . . . . . . . . . . . . . .32 COP Watchdog Timer Recommendations . . . . . . . . . . . . . . .44 Operating Mode Conditions . . . . . . . . . . . . . . . . . . . . . . . . . .45 I/O Pin Functions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .51 RTI Rates . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .56 PS1 and PS0 Speed Selects with 32.768-kHz Crystal. . . . . .62 COP Rates at fosc = 32.768 kHz. . . . . . . . . . . . . . . . . . . . . . .67 M-Bus Clock Prescaler . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .79 Master Mode SCK Frequency Select . . . . . . . . . . . . . . . . . .100 Register/Memory Instructions. . . . . . . . . . . . . . . . . . . . . . . .110 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . . .111 Jump and Branch Instructions . . . . . . . . . . . . . . . . . . . . . . .113 Bit Manipulation Instructions. . . . . . . . . . . . . . . . . . . . . . . . .114 Control Instructions. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . .116 Opcode Map . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .122 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 MC68HC05E5 -- Rev. 1.0 List of Tables For More Information On This Product, Go to: www.freescale.com General Release Specification NONDISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. List of Tables REQUIRED NONDISCLOSURE General Release Specification List of Tables For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 1. General Description 1.1 Contents 1.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .15 Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .16 Mask Options . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 Freescale Semiconductor, Inc... 1.3 1.4 1.2 Introduction The MC68HC05E5 is a low-cost introduction to the M68HC05 Family of microcontrollers (MCUs). The HC05 central processing unit (CPU) core has been enhanced with a 15-stage multifunctional timer and programmable phase-locked loop (PLL). The MCU is available in a 28-pin package and has two 8-bit input/output (I/O) ports and one 4-bit I/O port. The 8-Kbyte memory map includes 384 bytes of random access memory (RAM) and 5120 bytes of user read-only memory (ROM). The MC68HC705E5 serves as an erasable, programmable ROM (EPROM) based emulation device for the MC68HC05E5. MC68HC05E5 -- Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 1.5 Functional Pin Description . . . . . . . . . . . . . . . . . . . . . . . . . . . .18 1.5.1 VDD and VSS . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.2 IRQ . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .19 1.5.3 OSC1 and OSC2. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .20 1.5.4 RESET . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.5 PA0-PA7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.6 PB0-PB7. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.7 PC0-PC3 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .21 1.5.8 XFC . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 1.5.9 VDDSYN . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .22 AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED 1.3 Features Features of the MC68HC05E5 include: * * * * * * * * * * * * * * * * * * * * * Low Cost HC05 Core 28-Pin Package On-Chip Oscillator (Crystal or Ceramic Resonator) Phase-Locked Loop (PLL) Synthesizer with Programmable Speed Synchronous Serial Interface (SSI) with Interrupts and Most Significant Bit (MSB) or Least Significant Bit (LSB) First M-Bus (I2C) Communication Port 5120 Bytes of User ROM (Including 16 Bytes of User Vectors) 384 Bytes of On-Chip RAM 15-Stage Multifunctional Timer with Programmable Input Real-Time Interrupt Circuit Computer Operating Properly (COP) Watchdog Timer Mask Option Custom Periodic Interrupt Circuit 20 Bidirectional I/O Lines Single-Chip Mode Self-Check Mode Power-Saving Stop and Wait Modes Edge-Only Sensitive or Edge- and Level-Sensitive Interrupt Trigger Mask Option STOP Instruction Disable Mask Option System Control and Status Register Illegal Address Reset NON-DISCLOSURE General Release Specification Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. General Description Features COP SYSTEM OSC2 OSCILLATOR OSC1 CUSTOM PERIODIC INTERRUPT OSCOUT VDDSYN XFC I2C SYSTEM VDD VSS TPLL INTERNAL PROCESSOR CLOCK PLL SYNTHESIS CLOCK SELECT /2 SSI SYSTEM Freescale Semiconductor, Inc... PA0 DATA DIRECTION REGISTER PA1 PA2 PORT A PA3 PA4 PA5 PA6 PA7 PB0 STACK POINTER DATA DIRECTION REGISTER PROGRAM COUNTER CONDITION CODE REGISTER PB2 PORT B PB3/TIPL PB4/SCK PB5/SDI/SDO PB6/SDA PB7/SCL DATA DIRECTION REGISTER ROM -- 4608 BYTES PC0 PORT C PC1 PC2 PC3 RESET IRQ CPU CONTROL M68HC05 CPU CPU REGISTERS ALU ACCUMULATOR INDEX REGISTER SRAM -- 384 BYTES SELF-CHECK ROM -- 240 BYTES Figure 1-1. Block Diagram MC68HC05E5 -- Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE PB1 AGREEMENT TIMER SYSTEM REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED 1.4 Mask Options The M68HC05E5 has four mask options: 1. STOP instruction (enable/disable) 2. IRQ (edge-sensitive only or edge- and level-sensitive) 3. COP watchdog timer (enable/disable) 4. CPI Rate (1 second, 0.5 second, or 0.25 second) Freescale Semiconductor, Inc... AGREEMENT NOTE: A line over a signal name indicates an active low signal. For example, RESET is active low. 1.5 Functional Pin Description Figure 1-2 shows the single-chip mode pinout for the MC68HC05E5. Refer to the following subsections for a description of the pins. IRQ RESET OSC1 OSC2 PB7/SCL PB6/SDA PB5/SDIO PB4/SCK PB3/TIPL PB2 PB1 PB0 VDD VSS 1 2 3 4 5 6 7 8 9 10 11 12 13 14 28 27 26 25 24 23 22 21 20 19 18 17 16 15 XFC VDDSYN PA0 PA1 PA2 PA3 PA4 PA5 PA6 PA7 PC0 PC1 PC2 PC3 NON-DISCLOSURE Figure 1-2. Single-Chip Mode Pinout General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Description Functional Pin Description 1.5.1 VDD and VSS Power is supplied to the microcontroller using these two pins. VDD is the positive supply and VSS is ground. 1.5.2 IRQ The maskable interrupt request (IRQ) has a programmable option that provides two different choices of interrupt triggering sensitivity. The options are: 1. Negative edge-sensitive triggering only 2. Both negative edge-sensitive and level-sensitive triggering The MCU completes the current instruction before it responds to the interrupt request. When IRQ goes low for at least one tILIH, a logic 1 is latched internally to signify an interrupt has been requested. When the MCU completes its current instruction, the interrupt latch is tested. If the interrupt latch contains a logic 1, and the interrupt mask bit (I bit) in the condition code register is clear, the MCU then begins the interrupt sequence. If the option is selected to include level-sensitive triggering, the IRQ input requires an external resistor to VDD for wired-OR operation. The IRQ pin contains an internal Schmitt trigger as part of its input to improve noise immunity. Refer to Section 4. Interrupts for more detail. Freescale Semiconductor, Inc... NOTE: The voltage on the IRQ pin affects the mode of operation. For additional information, see Section 6. Operating Modes. MC68HC05E5 -- Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED 1.5.3 OSC1 and OSC2 These pins provide control input for an on-chip clock oscillator circuit which can optionally drive a PLL clock. A crystal, a ceramic resonator, or an external signal connects to these pins providing a system clock. The oscillator frequency is two times the internal bus rate if the PLL is not used. Crystal Figure 1-3 (a) shows the recommended circuit for using a crystal. The crystal and components should be mounted as close as possible to the input pins to minimize output distortion and startup stabilization time. Ceramic Resonator A ceramic resonator may be used in place of the crystal in cost-sensitive applications. Figure 1-3 (a) shows the recommended circuit for using a ceramic resonator. The manufacturer of the particular ceramic resonator being considered should be consulted for specific information. External Clock An external clock should be applied to the OSC1 input with the OSC2 pin not connected (refer to Figure 1-3 (b)). This setup can be used if the user does not wish to run the CPU with a 32.768-kHz crystal or the PLL frequencies are not suitable for the application. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT MCU OSC1 OSC2 330 k 20 M OSC1 MCU OSC2 UNCONNECTED 10 pF 32.768 kHz 33 pF < EXTERNAL CLOCK (a) Crystal/Ceramic Resonator Oscillator Connections (b) External Clock Source Connections Figure 1-3. Oscillator Connections General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Description Functional Pin Description 1.5.4 RESET This active low pin is used to reset the MCU to a known startup state by pulling RESET low. The RESET pin contains an internal Schmitt trigger as part of its input to improve noise immunity. See Section 5. Resets for additional information. 1.5.5 PA0-PA7 Freescale Semiconductor, Inc... 1.5.6 PB0-PB7 These eight I/O lines comprise port B. The state of any pin is software programmable and all port B lines are configured as input during power-on or reset. PB7 (SCL) and PB6 (SDA) can be configured as an M-bus interface. (Refer to Section 11. Motorola Bus (M Bus) Interface for M-bus pin configurations). PB3-PB5 (TIPL, SCK, and SDIO) can be configured as a synchronous serial interface (SSI). Refer to Section 12. Synchronous Serial Interface (SSI) and to 7.6 Input/Output Programming for additional information. 1.5.7 PC0-PC3 These four I/O lines comprise port C. The state of any pin is software programmable and all port C lines are configured as input during power-on or reset. 7.6 Input/Output Programming for additional information. MC68HC05E5 -- Rev. 1.0 General Description For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT These eight I/O lines comprise port A. The state of any pin is software programmable and all port A lines are configured as input during power-on or reset. See 7.6 Input/Output Programming for additional information. REQUIRED Freescale Semiconductor, Inc. General Description REQUIRED 1.5.8 XFC This pin provides a means for connecting an external filter capacitor to the synthesizer PLL filter. For additional information concerning this capacitor, see Section 9. Phase-Locked Loop (PLL) Synthesis. 1.5.9 VDDSYN This pin provides a separate power connection to the PLL synthesizer which should be at the same potential as VDD. Freescale Semiconductor, Inc... AGREEMENT NOTE: Any unused inputs and I/O ports should be tied to an appropriate logic level (either VDD or VSS). Although the I/O ports of the MC68HC05E5 do not require termination, it is recommended to reduce the possibility of static damage. NON-DISCLOSURE General Release Specification General Description For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 2. Memory 2.1 Contents 2.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 ROM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 RAM . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .23 Memory Map. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .24 Register Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .25 Freescale Semiconductor, Inc... 2.3 2.4 2.5 2.6 2.2 Introduction The MC68HC05E5 has an 8-Kbyte memory map, consisting of user read-only memory (ROM), user random access memory (RAM), self-check ROM, control registers, and input/output (I/O). Refer to Figure 2-1 for the memory map and Figure 2-2 for the register map. 2.3 ROM The user ROM consists of 5120 bytes located from $0B00 to $1EFF, with 16 additional bytes of user vectors from $1FF0 to $1FFF. The self-check ROM and vectors are located from $1F00 to $1FEF. 2.4 RAM The user RAM, including the stack area, consists of 384 bytes located from $0080 to $01FF. The stack begins at address $00FF. The stack pointer can access 64 bytes of RAM from $00FF to $00C0. Using the stack area for data storage or temporary work locations requires care to prevent it from being overwritten due to stacking from an interrupt or subroutine call. MC68HC05E5 -- Rev. 1.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Memory REQUIRED 2.5 Memory Map $0000 $001F $0020 $007F $0080 $00BF $00C0 0000 0031 0032 0127 0128 0191 0192 0255 0256 0511 0512 PORT A DATA REGISTER PORT B DATA REGISTER PORT C DATA REGISTER UNUSED PORT A DATA DIRECTION REGISTER PORT B DATA DIRECTION REGISTER PORT C DATA DIRECTION REGISTER PLL CONTROL REGISTER TIMER CONTROL & STATUS REGISTER TIMER COUNTER REGISTER SSI REGISTERS UNUSED 2815 2816 USER ROM 5120 BYTES $1EFF $1F00 SELF-CHECK ROM & VECTORS 240 BYTES USER VECTORS 16 BYTES 7935 7936 CPI CONTROL & STATUS REGISTER SCSR REGISTER I2C (M -BUS) REGISTERS $00 $01 $02 $03 $04 $05 $06 $07 $08 $09 $0A-$0C $0D-$11 $12 $13 $18 I/O 32 BYTES UNUSED 96 BYTES RAM 128 BYTES STACK 64 BYTES RAM 256 BYTES UNUSED 2304 BYTES Freescale Semiconductor, Inc... AGREEMENT $00FF $0100 $01FF $0200 $0AFF $0B00 ... $1C $1D $1E $1F UNUSED 8175 8176 8191 UNUSED UNUSED M BUS VECTOR (HIGH BYTE) M BUS VECTOR (LOW BYTE) SSI VECTOR (HIGH BYTE) SSI VECTOR (LOW BYTE) CPI VECTOR (HIGH BYTE) CPI VECTOR (LOW BYTE) TIMER VECTOR (HIGH BYTE) TIMER VECTOR (LOW BYTE) IRQ VECTOR (HIGH BYTE) IRQ VECTOR (LOW BYTE) SWI VECTOR (HIGH BYTE) SWI VECTOR (LOW BYTE) RESET VECTOR (HIGH BYTE) RESET VECTOR (LOW BYTE) $1FEF $1FF0 $1FFF RESERVED NON-DISCLOSURE ... $1FF0 $1FF1 $1FF2 $1FF3 $1FF4 $1FF5 $1FF6 $1FF7 $1FF8 $1FF9 $1FFA $1FFB $1FFC $1FFD $1FFE $1FFF Figure 2-1. Memory Map General Release Specification Memory For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Memory Register Summary 2.6 Register Summary Addr. $0000 $0001 $0002 $0003 Register Port A Data Register Port B Data Register Port C Data Register Unimplemented Port A Data Direction Register Port B Data Direction Register Port C Data Direction Register PLL Control Register Timer Control and Status Register. Timer Counter Register SSI Control Register SSI Status Register SSI Data Register Unimplemented Unimplemented Unimplemented Unimplemented Unimplemented CPI Control and Status Register. System Control and Status Register Unimplemented Unimplemented Unimplemented Unimplemented -- 0 CPIF 0 -- 0 CPIE STOPR -- ILADR -- COPR -- CRS1 -- CRS0 SIE SF D7 SE DCOL D6 LSBF 0 D5 MSTR 0 D4 CPOL 0 D3 SDIR 0 D2 SR1 0 D1 SR0 TIPL D0 0 TOF BCS RTIF 0 TOFE BWC RTIE PLLON TOFA VCOTST RTIFA PS1 RT1 PS0 RT0 0 0 0 0 Bit 7 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... $0004 $0005 $0006 $0007 $0008 $0009 $000A $000B $000C $000D $000E $000F $0010 $0011 $0012 $0013 $0014 $0015 $0016 $0017 = Unimplemented Figure 2-2. I/O Registers MC68HC05E5 -- Rev. 1.0 Memory For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Memory REQUIRED Addr. $0018 $0019 $001A $001B $001C $001D Register M-Bus Address Register M Bus Frequency Divider Register M Bus Control Register M Bus Status Register M Bus Data I/O Register Unimplemented Unimplemented Reserved Bit 7 MAD7 6 MAD6 5 MAD5 4 MAD4 FD4 3 MAD3 FD3 TXAK 2 MAD2 FD2 MMUX SRW 1 MAD1 FD1 Bit 0 FD0 MEN MCF MD7 MIEN MAAS MD6 MSTA MBB MD5 MTX MAL MD4 MIF MD1 MXAK MD0 MD3 MD2 Freescale Semiconductor, Inc... AGREEMENT $001E $001F R R R R R R R R = Unimplemented R = Reserved Figure 2-2. I/O Registers (Continued) NON-DISCLOSURE General Release Specification Memory For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 3. Central Processing Unit (CPU) 3.1 Contents 3.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .27 Accumulator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Index Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .28 Condition Code Register. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .29 Stack Pointer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Program Counter . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .30 Freescale Semiconductor, Inc... 3.3 3.4 3.5 3.6 3.7 3.2 Introduction The MCU contains five registers as shown in Figure 3-1. The interrupt stacking order is shown in Figure 3-2. 7 A 7 X 12 PC 12 0 0 0 0 0 7 1 1 SP CCR H I N Z C CONDITION CODE REGISTER 0 STACK POINTER 0 PROGRAM COUNTER 0 INDEX REGISTER 0 ACCUMULATOR Figure 3-1. Programming Model MC68HC05E5 -- Rev. 1.0 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Central Processing Unit (CPU) REQUIRED 7 1 INCREASING MEMORY ADDRESSES R E T U R N 1 1 0 CONDITION CODE REGISTER ACCUMULATOR INDEX REGISTER PCH PCL UNSTACK NOTE: Since the stack pointer decrements during pushes, the PCL is stacked first, followed by PCH, etc. Pulling from the stack is in the reverse order. STACK I N T E R R U P T DECREASING MEMORY ADDRESSES Freescale Semiconductor, Inc... AGREEMENT Figure 3-2. Stacking Order 3.3 Accumulator The accumulator is a general-purpose 8-bit register used to hold operands and results of arithmetic calculations or data manipulations. Bit 7 6 5 4 A 3 2 1 Bit 0 Figure 3-3. Accumulator (A) NON-DISCLOSURE 3.4 Index Register The index register is an 8-bit register used for the indexed addressing value to create an effective address. The index register may also be used as a temporary storage area. Bit 7 6 5 4 X 3 2 1 Bit 0 Figure 3-4. Index Register (X) General Release Specification Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Central Processing Unit (CPU) Condition Code Register 3.5 Condition Code Register The CCR is a 5-bit register in which the H, N, Z, and C bits are used to indicate the results of the instruction just executed, and the I bit is used to enable interrupts. These bits can be tested individually by a program, and specific actions can be taken as a result of their state. Each bit is explained in the following paragraphs. Bit 4 3 I 2 N 1 Z Bit 0 Freescale Semiconductor, Inc... Figure 3-5. Condition Code Register (CCR) Half Carry (H) This bit is set during ADD and ADC operations to indicate that a carry occurred between bits 3 and 4. Interrupt (I) When this bit is set, the timer and external interrupt are masked (disabled). If an interrupt occurs while this bit is set, the interrupt is latched and processed as soon as the I bit is cleared. Negative (N) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was negative. Zero (Z) When set, this bit indicates that the result of the last arithmetic, logical, or data manipulation was zero. Carry/Borrow (C) When set, this bit indicates that a carry or borrow out of the arithmetic logical unit (ALU) occurred during the last arithmetic operation. This bit also is affected during bit test and branch instructions and during shifts and rotates. MC68HC05E5 -- Rev. 1.0 Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT H C REQUIRED Freescale Semiconductor, Inc. Central Processing Unit (CPU) REQUIRED 3.6 Stack Pointer The stack pointer contains the address of the next free location on the stack. During an MCU reset or the reset stack pointer (RSP) instruction, the stack pointer is set to location $00FF. The stack pointer then is decremented as data is pushed onto the stack and incremented as data is pulled from the stack. When accessing memory, the seven most significant bits (MSB) are permanently set to 0000011. These seven bits are appended to the six least significant register bits to produce an address within the range of $00FF to $00C0. Subroutines and interrupts may use up to 64 (decimal) locations. If 64 locations are exceeded, the stack pointer wraps around and loses the previously stored information. A subroutine call occupies two locations on the stack; an interrupt uses five locations. Bit 12 0 Bit 0 Freescale Semiconductor, Inc... AGREEMENT 11 0 10 0 9 0 8 0 7 1 6 5 4 3 SP 2 1 Figure 3-6. Stack Pointer (SP) NON-DISCLOSURE 3.7 Program Counter The program counter is a 13-bit register that contains the address of the next byte to be fetched. Bit 12 Bit 0 11 10 9 8 7 6 PC 5 4 3 2 1 Figure 3-7. Program Counter (PC) NOTE: The HC05 CPU core is capable of addressing 16-bit locations. For this implementation, however, the addressing registers are limited to an 8-Kbyte memory map. General Release Specification Central Processing Unit (CPU) For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 4. Interrupts 4.1 Contents 4.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .31 Hardware Controlled Interrupt Sequence . . . . . . . . . . . . . . . . .33 Software Interrupt (SWI) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .33 External Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Timer Interrupt . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .34 Custom Periodic Interrupt (CPI) . . . . . . . . . . . . . . . . . . . . . . . .37 Synchronous Serial Interface Interrupt (SSI) . . . . . . . . . . . . . .38 M-Bus (I2C) Interrupt (M Bus). . . . . . . . . . . . . . . . . . . . . . . . . .38 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .38 Freescale Semiconductor, Inc... 4.3 4.4 4.5 4.6 4.7 4.8 4.9 4.10 4.11 4.2 Introduction The MCU can be interrupted six different ways: the five maskable hardware interrupts (IRQ, timer, CPI, SSI, and M bus) and the nonmaskable software interrupt instruction (SWI). Interrupts cause the processor to save register contents on the stack and to set the interrupt mask (I bit) to prevent additional interrupts. The RTI instruction causes the register contents to be recovered from the stack and normal processing to resume. MC68HC05E5 -- Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .38 AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED Unlike RESET, hardware interrupts do not cause the current instruction execution to be halted, but are considered pending until the current instruction is complete. The current instruction is the one already fetched and being operated on. When the current instruction is complete, the processor checks all pending hardware interrupts. If interrupts are not masked (CCR I bit clear) and the corresponding interrupt enable bit is set, the processor proceeds with interrupt processing; otherwise, the next instruction is fetched and executed. If both an external interrupt and a timer interrupt are pending at the end of an instruction execution, the external interrupt is serviced first. The SWI is executed the same as any other instruction, regardless of the I-bit state. Freescale Semiconductor, Inc... AGREEMENT Table 4-1. Vector Address for Interrupts and Reset Register N/A N/A N/A TCSR N/A CPICSR SSR MSR Flag Name N/A N/A N/A TOF RTIF CPIF SF MIF Reset Software External Interrupt Timer Overflow Real-Time Interrupt Custom Periodic Interrupt Synchronous Serial Interrupt M-Bus Interrupt Interrupts CPU Interrupt RESET SWI IRQ TIMER TIMER CPI SSI M Bus Vector Address $1FFE-$1FFF $1FFC-$1FFD $1FFA-$1FFB $1FF8-$1FF9 $1FF8-$1FF9 $1FF6-$1FF7 $1FF4-$1FF5 $1FF2-$1FF3 NON-DISCLOSURE General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Interrupts Hardware Controlled Interrupt Sequence 4.3 Hardware Controlled Interrupt Sequence The following three functions (RESET, STOP, and WAIT) are not in the strictest sense an interrupt; however, they are acted upon in a similar manner. See Figure 4-1 and Figure 4-2. A discussion is provided below. 1. RESET -- A low input on the RESET input pin causes the program to vector to its starting address which is specified by the contents of memory locations $1FFE and $1FFF. The I bit in the condition code register is also set. Much of the MCU is configured to a known state during this type of reset as described in Section 5. Resets. 2. STOP -- The STOP instruction causes the oscillator to be turned off and the processor to "sleep" until an external interrupt (IRQ) or reset occurs. 3. WAIT -- The WAIT instruction causes all processor clocks to stop, but leaves the timer clock running. This "rest" state of the processor can be cleared by reset, an external interrupt (IRQ), or timer interrupt. There are no special wait vectors for these individual interrupts. Freescale Semiconductor, Inc... The SWI is an executable instruction and a nonmaskable interrupt. It is executed regardless of the state of the I bit in the CCR. If the I bit is zero (interrupts enabled), SWI executes after interrupts which were pending when the SWI was fetched but before interrupts generated after the SWI was fetched. The interrupt service routine address is specified by the contents of memory locations $1FFC and $1FFD. MC68HC05E5 -- Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 4.4 Software Interrupt (SWI) AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED 4.5 External Interrupt If the I bit of the condition code reister (CCR) is set, all maskable interrupts (internal and external) are disabled. Clearing the I bit enables interrupts. The interrupt request is latched immediately following the falling edge of IRQ. It is then synchronized internally and serviced by the interrupt service routine located at the address specified by the contents of $1FFA and $1FFB. Either a level-sensitive and edge-sensitive trigger or an edge-sensitive-only trigger is available as a mask option. Freescale Semiconductor, Inc... AGREEMENT NOTE: The internal interrupt latch is cleared in the first part of the interrupt service routine; therefore, one external interrupt pulse could be latched and serviced as soon as the I bit is cleared. 4.6 Timer Interrupt Two different timer interrupt flags cause a timer interrupt whenever they are set and enabled. The interrupt flags and enable bits are located in the timer control and status register (TCSR). Either of these interrupts will vector to the same interrupt service routine, located at the address specified by the contents of memory location $1FF8 and $1FF9. For additional information, refer to 8.3 Timer Control and Status Register. NON-DISCLOSURE General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Interrupts Timer Interrupt FROM RESET Y IS I BIT SET? N IRQ EXTERNAL INTERRUPT? N TIMER INTERNAL INTERRUPT? N CPI INTERNAL INTERRUPT? N LOAD PC FROM: SWI: $1FFC-$1FFD IRQ: $1FFA-$1FFB TIMER: $1FF8-$1FF9 CPI: $1FF6-$1FF7 SSI: $1FF4-$1FF5 M BUS: $1FF2-$1FF3 Y CLEAR IRQ REQUEST LATCH. Freescale Semiconductor, Inc... Y Y STACK PC, X, A, CC. Y SET I BIT. N SWI INSTRUCTION ? N RTI INSTRUCTION ? N EXECUTE INSTRUCTION. Y RESTORE RESISTERS FROM STACK CC, A, X, PC Figure 4-1. Interrupt Processing Flowchart MC68HC05E5 -- Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE FETCH NEXT INSTRUCTION. AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED STOP WAIT STOP OSCILLATOR AND ALL CLOCKS. CLEAR I BIT. OSCILLATOR ACTIVE. TIMER CLOCK ACTIVE. PROCESSOR CLOCKS STOPPED. AGREEMENT N Freescale Semiconductor, Inc... RESET? RESET? N N EXTERNAL INTERRUPT (IRQ)? Y Y Y EXTERNAL INTERRUPT (IRQ)? Y N TIMER INTERNAL Y INTERRUPT? Y N TURN ON OSCILLATOR. WAIT FOR TIME DELAY TO STABILIZE. RESTART PROCESSOR CLOCK. CPI, SSI, OR M-BUS INTERNAL INTERRUPT? Y N NON-DISCLOSURE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE 1. FETCH RESET VECTOR OR 2. SERVICE INTERRUPT A. STACK B. SET I BIT C. VECTOR TO INTERRUPT ROUTINE Figure 4-2. STOP/WAIT Flowcharts General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Interrupts Custom Periodic Interrupt (CPI) 4.7 Custom Periodic Interrupt (CPI) The CPI flag and enable bits are located in the CPI control and status register (CPICSR). A CPI interrupt will vector to the interrupt service routine located at the address specified by the contents of memory location $1FF6 and $1FF7. The custom periodic interrupt is mask programmable to a 0.25 second, 0.5 second, or 1 second interrupt. The interrupt is generated from the 32-kHz OSC1 input by a 15-bit counter. This interrupt is under the control of the custom periodic interrupt control and status register located at $12. Address $0012 Bit 7 Read: 0 Write: Reset: 0 0 0 0 0 0 0 0 CPIF 0 CPIE 0 0 0 0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Figure 4-3. Custom Periodic Interrupt Control and Status Register (CPICSR) CPIF -- Custom Periodic Interrupt Flag CPIF is a clearable, read-only status bit and is set when the 15-bit counter changes from $7FFF to $0000. A CPU interrupt request will be generated if CPIE is set. Clearing the CPIF is done by writing a zero to it. Writing a one to CPIF has no effect on the bit's value. Reset clears CPIF. CPIE -- Custom Periodic Interrupt Enable When this bit is cleared, the CPI interrupts are disabled. When this bit is set, the CPU interrupt request is generated when the CPIF bit is set. Reset clears this bit. MC68HC05E5 -- Rev. 1.0 Interrupts For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Interrupts REQUIRED 4.8 Synchronous Serial Interface Interrupt (SSI) The SSI flag and enable bits are located in the SSI control (SCR) and status (SSR) registers. An SSI interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1FF4 and $1FF5. For additional information, refer to 12.4 SSI Registers. Freescale Semiconductor, Inc... AGREEMENT 4.9 M-Bus (I2C) Interrupt (M Bus) The MIF flag and enable bits are located in the M-bus status (MSR) and control (MCR) registers. An M-bus interrupt will vector to the interrupt service routine located at the address specified by the contents of memory locations $1FF2 and $1FF3. For further information, refer to 11.6 M-Bus Registers. 4.10 Operation During Stop Mode The timer system is cleared and the CPI counter is halted when going into stop mode. When stop mode is exited by an external interrupt or an external RESET, the internal oscillator will resume, followed by a 4064-cycle internal processor oscillator stabilization delay. The timer system counter is then cleared and operation resumes. The CPI will continue counting once the oscillator resumes and does not wait for the oscillator to stabilize. NON-DISCLOSURE 4.11 Operation During Wait Mode The CPU clock halts during wait mode, but the timer and CPI remain active. A timer interrupt or custom periodic interrupt, SSI, and M bus will cause the processor to exit wait mode if the interrupts are enabled. General Release Specification Interrupts For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 5. Resets 5.1 Contents 5.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .39 External Reset (RESET). . . . . . . . . . . . . . . . . . . . . . . . . . . . . .40 Internal Resets . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Power-On Reset (POR) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .42 Freescale Semiconductor, Inc... 5.3 5.4 5.5 5.6 Computer Operating Properly Reset (COPR). . . . . . . . . . . . . .43 5.6.1 Resetting the COP . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.6.2 COP During Wait Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.6.3 COP During Stop Mode. . . . . . . . . . . . . . . . . . . . . . . . . . . .43 5.6.4 COP Watchdog Timer Considerations . . . . . . . . . . . . . . . .44 5.7 Illegal Address Reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .44 5.2 Introduction The MCU can be reset from five sources: one external input and four internal restart conditions. The RESET pin is an input with a Schmitt trigger as shown in Figure 5-1. All the internal peripheral modules will be reset by the internal reset signal (RST). Refer to Figure 5-2 for reset timing detail. MC68HC05E5 -- Rev. 1.0 Resets For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED 5.3 External Reset (RESET) The RESET pin is the only external source of a reset. This pin is connected to a Schmitt trigger input gate to provide an upper and lower threshold voltage separated by a minimum amount of hysteresis. This external reset occurs whenever the RESET pin is pulled below the lower threshold and remains in reset until the RESET pin rises above the upper threshold. This active-low input will generate the RST signal and reset the CPU and peripherals. The only reset sources that can alter the MCU's operating mode are termination of the external reset input or the internal computer operating properly (COP) watchdog reset. Freescale Semiconductor, Inc... AGREEMENT NOTE: Activation of the RST signal is generally referred to as a reset of the device, unless otherwise specified. IRQ/VTST D LATCH RESET (PULSE WIDTH = 3 x E-CLK) PH2 OSC DATA ADDRESS CLOCKED ONE-SHOT R TO IRQ LOGIC MODE SELECT NON-DISCLOSURE COP WATCHDOG (COPR) CPU POWER-ON RESET (POR) ILLEGAL ADDRESS (ILLADDR) DISABLED STOP INSTRUCTION PH2 S D LATCH TO OTHER PERIPHERALS VDD RST ADDRESS STOPEN Figure 5-1. Reset Block Diagram General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc... tVDDR MC68HC05E5 -- Rev. 1.0 4064 tcyc tcyc 1FFE 1FFF 1FFE 1FFE NEW PC NEW PC 1FFE 1FFE 1FFF NEW PC NEW PC NEW PCH NEW PCL tRL 3 OP CODE PCH PCL OP CODE VDD VDD THRESHOLD (1 TO 2 V TYPICAL) OSC12 INTERNAL PROCESSOR CLOCK1 INTERNAL ADDRESS BUS1 INTERNAL DATA BUS1 Freescale Semiconductor, Inc. Resets For More Information On This Product, Go to: www.freescale.com RESET NOTES: 1. Internal timing signal and bus information are not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. General Release Specification Resets External Reset (RESET) Figure 5-2. RESET and POR Timing Diagram NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED The RESET pin can also act as an open-drain output. It will be pulled to a low state by an internal pulldown that is activated by any reset source. This RESET pulldown device will be asserted only by three to four cycles of the internal clock, PH2 (PH2 period = E clock period), or as long as an internal reset source is asserted. When the external RESET pin is asserted, the pulldown device will be turned on for the three to four internal clock cycles only. Freescale Semiconductor, Inc... AGREEMENT 5.4 Internal Resets The four internally generated resets are the initial power-on reset function, the COP watchdog timer reset, the illegal address detector, and the disabled STOP instruction. The only reset sources that can alter the MCU's operating mode are termination of the external RESET input or the internal COP watchdog timer. The other internal resets will not have any effect on the mode of operation when their reset state ends. All internal resets will also assert (pull to logic 0) the external RESET pin for the duration of the reset or three to four internal clock cycles, whichever is longer. NON-DISCLOSURE 5.5 Power-On Reset (POR) The internal POR is generated on power-up to allow the clock oscillator to stabilize. The POR is strictly for power turn-on conditions and is not able to detect a drop in the power supply voltage (brown-out). There is an oscillator stabilization delay of 4064 internal processor clock cycles after the oscillator becomes active. The POR will generate the RST signal which will reset the CPU. If any other reset function is active at the end of the 4064-cycle delay, the RST signal will remain in the reset condition until the other reset condition(s) end. POR will activate the RESET pin pulldown device connected to the pin. VDD must drop below VPOR for the internal POR circuit to detect the next rise of VDD. General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Resets Computer Operating Properly Reset (COPR) 5.6 Computer Operating Properly Reset (COPR) The MCU contains a watchdog timer that automatically times out if not reset (cleared) within a specific time by a program reset sequence. If the COP watchdog timer is allowed to timeout, an internal reset is generated to reset the MCU. Regardless of an internal or external reset, the MCU comes out of a COP reset according to the standard rules of mode selection. The COP reset function is enabled or disabled by a mask option and is verified during production testing. The COP watchdog reset will activate the internal pulldown device connected to the RESET pin. Freescale Semiconductor, Inc... 5.6.1 Resetting the COP Preventing a COP reset is done by writing a logic 0 to the COPF bit. This action will reset the counter and begin the timeout period again. The COPF bit is bit 0 of address $1FF0. A read of address $1FF0 will return user data programmed at that location. 5.6.2 COP During Wait Mode The COP will continue to operate normally during wait mode. The software should pull the device out of wait mode periodically and reset the COP by writing to the COPF bit to prevent a COP reset. 5.6.3 COP During Stop Mode When the stop enable mask option is selected, stop mode disables the oscillator circuit and thereby turns the clock off for the entire device. The COP counter will be reset when stop mode is entered. If a reset is used to exit stop mode, the COP counter will be held in reset during the 4064 cycles of startup delay. If any operable interrupt is used to exit stop mode, the COP counter will not be reset during the 4064-cycle startup delay and will have that many cycles already counted when control is returned to the program. MC68HC05E5 -- Rev. 1.0 Resets For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Resets REQUIRED 5.6.4 COP Watchdog Timer Considerations If enabled by a mask option, the COP watchdog timer is active in all modes of operation (disabled in test and self-check modes). If the COP watchdog timer is selected by a mask option, any execution of the STOP instruction (either intentional or inadvertent due to the CPU being disturbed) will cause the oscillator to halt and prevent the COP watchdog timer from timing out. Therefore, it is recommended that the STOP instruction should be disabled if the COP watchdog timer is enabled. If the COP watchdog timer is selected by a mask option, the COP will reset the MCU when it times out. Therefore, it is recommended that the COP watchdog should be disabled for a system that must have intentional uses of the wait mode for periods longer than the COP timeout period. The recommended interactions and considerations for the COP watchdog timer, STOP instruction, and WAIT instruction are summarized in Figure 5-1. Table 5-1. COP Watchdog Timer Recommendations IF the Following Conditions Exist: STOP Instruction Converted to Reset Wait Time WAIT Time Less Than COP Timeout WAIT Time More Than COP Timeout Any Length WAIT Time THEN the COP Watchdog Timer Should Be: Enable or Disable COP by Mask Option NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT Converted to Reset Disable COP by Mask Option Acts as STOP Disable COP by Mask Option 5.7 Illegal Address Reset When an opcode fetch occurs from an address which is not implemented in the RAM ($0080-$01FF) or ROM ($0F00-$1FFF), the part is reset automatically. General Release Specification Resets For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 6. Operating Modes 6.1 Contents 6.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .45 Single-Chip Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Self-Check Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 Freescale Semiconductor, Inc... 6.3 6.4 6.5 Low-Power Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.5.1 Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .46 6.5.2 Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.5.3 Data-Retention Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . .47 6.2 Introduction The MCU has two modes of operation: single-chip mode and self-check mode. This section describes these modes as well as the two low-power modes: stop mode and wait mode. Refer to Table 6-1 for the conditions required to go into each of the operating modes. Table 6-1. Operating Mode Conditions RESET IRQ VSS - VDD VTST VTST = 2 x VDD PB1 VSS - VDD VDD Mode Single-Chip Self-Check MC68HC05E5 -- Rev. 1.0 Operating Modes For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Operating Modes REQUIRED 6.3 Single-Chip Mode In single-chip mode, the address and data buses are not available externally, but there are two 8-bit input/output (I/O) ports and one 4-bit I/O port. This mode allows the MCU to function as a self-contained microcontroller, with maximum use of the pins for on-chip peripheral functions. All address and data activity occurs within the MCU. Single-chip mode is entered on the rising edge of RESET if the IRQ pin is within normal operating range. Refer to Figure 1-2 for the single-chip user mode pinout diagram. Freescale Semiconductor, Inc... AGREEMENT 6.4 Self-Check Mode The self-check mode provides an internal check to determine if the device is functional. 6.5 Low-Power Modes The following subsections provide a description of the low-power modes. NON-DISCLOSURE 6.5.1 Stop Mode The STOP instruction places the MCU in its lowest power-consumption mode. In stop mode, the internal oscillator is turned off, halting all internal processing, including timer (and COP watchdog timer) operation. During stop mode, the I bit in the CCR is cleared to enable external interrupts. All other registers, including the bits in the TCSR, and memory remain unaltered. All input/output lines remain unchanged. The processor can be brought out of stop mode only by an external interrupt or RESET. The STOP instruction can be disabled by a mask option. When disabled, the STOP instruction causes a chip reset. General Release Specification Operating Modes For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Operating Modes Low-Power Modes Refer to Figure 4-2 and to 4.10 Operation During Stop Mode for additional information. 6.5.2 Wait Mode The WAIT instruction places the MCU in a low power-consumption mode, but the wait mode consumes more power than the stop mode. All CPU action is suspended, but the timer, CPI, COP, SSI, and M bus remain active. An interrupt from the timer, SSI, or M bus can cause the MCU to exit the wait mode. During the wait mode, the I bit in the CCR is cleared to enable interrupts. All other registers, memory, and input/output lines remain in their previous state. The timer, SSI, and/or IIC modules may be enabled to allow a periodic exit from the wait mode. Refer to Figure 4-2 and to 4.11 Operation During Wait Mode for additional information. Freescale Semiconductor, Inc... 6.5.3 Data-Retention Mode The contents of RAM and CPU registers are retained at supply voltages as low as 2.0 Vdc. This is called the data-retention mode where the data is held, but the device is not guaranteed to operate. RESET must be held low during data-retention mode. MC68HC05E5 -- Rev. 1.0 Operating Modes For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Operating Modes REQUIRED NON-DISCLOSURE General Release Specification Operating Modes For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 7. Input/Output (I/O) Ports 7.1 Contents 7.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Port A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .49 Port B . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Port C . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Input/Output Programming . . . . . . . . . . . . . . . . . . . . . . . . . . . .50 Freescale Semiconductor, Inc... 7.3 7.4 7.5 7.6 7.2 Introduction In single-chip mode, 20 lines are arranged as two 8-bit input/output (I/O) ports and one 4-bit I/O port. These ports are programmable as either inputs or outputs under software control of the data direction registers. To avoid a glitch on the output pins, write data to the I/O port data register before writing a one to the corresponding data direction register (DDR). 7.3 Port A Port A is an 8-bit bidirectional port which does not share any of its pins with other subsystems. The port A data register is at $0000 and the DDR is at $0004. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. MC68HC05E5 -- Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Input/Output (I/O) Ports REQUIRED 7.4 Port B Port B is an 8-bit bidirectional port which does share some of its pins with other subsystems. The address of the port B data register is $0001 and the DDR is at address $0005. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. Refer to Section 11. Motorola Bus (M Bus) Interface and Section 12. Synchronous Serial Interface (SSI) for descriptions of port B behavior while either module is enabled. Freescale Semiconductor, Inc... AGREEMENT 7.5 Port C Port C is a 4-bit bidirectional port which does not share any of its pins with other subsystems. The port C data register is at $0002 and the DDR is at $0006. Reset does not affect the data registers, but clears the data direction registers, thereby returning the ports to inputs. Writing a one to a DDR bit sets the corresponding port bit to output mode. 7.6 Input/Output Programming Ports A, B, and C may be programmed as inputs or outputs under software control. The direction of the pins is determined by the state of the corresponding bit in the port DDR with each port having an associated DDR. Any port A, port B, or port C pin is configured as an output if its corresponding DDR bit is set to a logic 1. A pin is configured as an input if its corresponding DDR bit is cleared to a logic 0. At power-on or reset, all DDRs are cleared, which configures all port A, B, and C pins as inputs. The data direction registers are capable of being written to or read from by the processor. During the programmed output state, a read of the data register actually reads the value of the output data latch and not the I/O pin. See Table 7-1 and Figure 7-1. NON-DISCLOSURE General Release Specification Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Input/Output (I/O) Ports Input/Output Programming Table 7-1. I/O Pin Functions R/W 0 0 1 1 DDR 0 1 0 1 I/O Pin Function The I/O pin is in input mode. Data is written into the output data latch. Data is written into the output data latch and output of the I/O pin. The state of the I/O pin is read. The I/O pin is in an output mode. The output data latch is read. Freescale Semiconductor, Inc... DATA DIRECTION REGISTER BIT INTERNAL HC05 CONNECTIONS LATCHED OUTPUT DATA BIT INPUT REGISTER BIT OUTPUT I/O PIN INPUT I/O Figure 7-1. Port I/O Circuitry MC68HC05E5 -- Rev. 1.0 Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Input/Output (I/O) Ports REQUIRED NON-DISCLOSURE General Release Specification Input/Output (I/O) Ports For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 8. Timer 8.1 Contents 8.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .53 Timer Control and Status Register . . . . . . . . . . . . . . . . . . . . . .55 Timer Counter Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .57 Freescale Semiconductor, Inc... 8.3 8.4 8.2 Introduction The timer for this device is a 15-stage multifunctional ripple counter. The features include timer overflow, power-on reset (POR), and real-time interrupt. As seen in Figure 8-1, the timer is driven by the output of the clock select circuit (as determined by the value of BCS in the PLLCR) and then a fixed divide-by-four prescaler. This signal drives an 8-bit ripple counter. The value of this 8-bit ripple counter can be read by the CPU at any time by accessing the timer counter register (TCR) at address $09. A timer overflow function is implemented on the last stage of this counter, giving a possible interrupt at the rate of fop/1024. Two additional stages produce the POR function at fop/4064. This circuit is followed by two more stages, with the resulting clock (fop/16,384) driving the real-time interrupt circuit. The RTI circuit consists of three divider stages with a one-of-four selector. The RTI rate selector bit and the RTI and TOF enable bits and flags are located in the timer control and status register at location $0008. MC68HC05E5 -- Rev. 1.0 Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Timer REQUIRED MC68HC05E4 INTERNAL BUS 8 8 INTERNAL PROCESSOR CLOCK /4 $09 TCR TIMER COUNTER REGISTER (TCR) TCR fop/210 fop fop/22 Freescale Semiconductor, Inc... AGREEMENT 7-BIT COUNTER POR TCBP RTI SELECT CIRCUIT OVERFLOW DETECT CIRCUIT $08 TCSR TIMER CONTROL & STATUS REGISTER TCSR TOF RTIF TOFE RTIE TOFA RTIFA RT1 RT0 NON-DISCLOSURE INTERRUPT CIRCUIT TO INTERRUPT LOGIC Figure 8-1. Timer Block Diagram General Release Specification Timer For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Timer Timer Control and Status Register 8.3 Timer Control and Status Register The timer control and status register (TCSR) contains the timer interrupt flag, the timer interrupt enable bits, and the real-time interrupt rate select bits. Figure 8-2 shows the value of each bit in the TCSR when coming out of reset. Address: $0008 Bit 7 6 RTIF 0 5 TOFE 0 4 RTIE 0 3 TOFA 0 2 RTIFA 0 1 RT1 1 Bit 0 RT0 1 Freescale Semiconductor, Inc... TOF Write: Reset: 0 Figure 8-2. Timer Control and Status Register (TCSR) TOF -- Timer Over Flow TOF is a clearable, read-only status bit and is set when the 8-bit ripple counter rolls over from $FF to $00. A CPU interrupt request will be generated if TOFE is set. Clearing the TOF is done by writing a logic 1 to TOFA. This is a read-only bit. Reset also clears TOF. RTIF -- Real-Time Interrupt Flag The real-time interrupt circuit consists of a 3-stage divider and a one-of-four selector. The clock frequency that drives the RTI circuit is fop/213 (or fop/8192) with three additional divider stages giving a maximum interrupt period of four seconds at a crystal frequency of 32.768 kHz. RTIF is a clearable, read-only status bit and is set when the output of the chosen (one-of-four selection) stage goes active. A CPU interrupt request will be generated if RTIE is set. Clearing the RTIF is done by writing a logic 1 to RTIFA. Reset also clears RTIF. TOFE -- Timer Overflow Enable When this bit is set, a CPU interrupt request is generated when the TOF bit is set. Reset clears this bit. MC68HC05E5 -- Rev. 1.0 Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT Read: REQUIRED Freescale Semiconductor, Inc. Timer REQUIRED RTIE -- Real-Time Interrupt Enable When this bit is set, a CPU interrupt request is generated when the RTIF bit is set. Reset clears this bit. TOFA -- Timer Over Flow Flag Acknowledge When a one is written to this bit location, the TOF flag bit is cleared. This bit always reads as a zero. RTIFA -- Real-Time Interrupt Flag Acknowledge Freescale Semiconductor, Inc... AGREEMENT When a one is written to this bit location, the RTIF flag bit is cleared. This bit always reads as a zero. RT1-RT0 -- Real-Time Interrupt Rate Select These two bits select one of four taps from the real-time interrupt circuit.Table 8-1 shows the available interrupt rates with several fop values. Reset sets RT0 and RT1, selecting the lowest periodic rate and therefore the maximum time in which to alter these bits if necessary. Care should be taken when altering RT0 and RT1 if the time-out period is imminent or uncertain. If the selected tap is modified during a cycle in which the counter is switching, an RTIF could be missed or an additional one could be generated. Table 8-1. RTI Rates RT1 Rates at fop Frequency Specified: RT1flRT0 16.384 kHz 00 01 10 11 1s 2s 4s 8s 524 kHz 31.3 ms 62.5 ms 125 ms 250 ms 1.049 MHz 15.6 ms 31.3 ms 62.5 ms 125.1 ms 2.097 MHz 7.8 ms 15.6 ms 31.3 ms 62.5 ms 4.194 MHz 3.9 ms 7.8 ms 15.6 ms 31.3 ms fop 214 / fop 215 / fop 216 / fop 217 / fop NON-DISCLOSURE General Release Specification Timer For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Timer Timer Counter Register 8.4 Timer Counter Register The timer counter register (TCR) is a read-only register which contains the current value of the 8-bit ripple counter at the beginning of the timer chain. This counter is clocked at fop divided by four and can be used for various functions including a software input capture. Extended time periods can be attained using the TOF function to increment a temporary RAM storage location, thereby simulating a 16-bit (or more) counter. Address: $0009 Bit 7 Read: Write: Reset: 0 0 0 0 0 0 1 1 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... = Unimplemented Figure 8-3. Timer Counter Register (TCR) The power-on cycle clears the entire counter chain and begins clocking the counter. After 4064 cycles, the power-on reset circuit is released which again clears the counter chain and allows the device to come out of reset. At this point, if RESET is not asserted, the timer will start counting up from zero and normal device operation will begin. When RESET is asserted any time during operation other than POR, the counter chain will be cleared. MC68HC05E5 -- Rev. 1.0 Timer For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Timer REQUIRED NON-DISCLOSURE General Release Specification Timer For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 9. Phase-Locked Loop (PLL) Synthesis 9.1 Contents 9.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .59 Phase-Locked Loop Control Register. . . . . . . . . . . . . . . . . . . .61 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .63 Noise Immunity . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .63 Freescale Semiconductor, Inc... 9.3 9.4 9.5 9.2 Introduction The PLL consists of a variable bandwidth loop filter, a voltage-controlled oscillator (VCO), a feedback frequency divider, and a digital phase detector. The PLL requires an external loop filter capacitor (typically 0.1 F) connected between XFC and VDDSYN. This capacitor should be located as close to the chip as possible to minimize noise. VDDSYN is the supply source for the PLL and should be bypassed to minimize noise. The VDDSYN bypass cap should be as close as possible to the chip. The phase detector compares the frequency and phase of the feedback frequency (tFB) and the crystal oscillator reference frequency (tREF) and generates the output, PCOMP, as shown in Figure 9-1. The output waveform is then integrated and amplified. The resultant DC voltage is applied to the voltage controlled oscillator. The output of the VCO is divided by a variable frequency divider of 256, 128, 64, or 32 to provide the feedback frequency for the phase detector. MC68HC05E5 -- Rev. 1.0 Phase-Locked Loop (PLL) Synthesis For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesis REQUIRED VDDSYN 0.1 F 0.1 F XFC LOOP FILTER VCO PLLOUT OSC1 CLOCK SELECT /2 TO CLOCK GENERATION CIRCUITRY tREF OSC1 CRYSTAL OSCILLATOR PHASE DETECT PCOMP BCS Freescale Semiconductor, Inc... AGREEMENT tFB FREQUENCY DIVIDER PS1 PS0 Figure 9-1. PLL Circuit To change PLL frequencies, follow the procedure outlined here: 1. Clear BCS to enable the low-frequency bus rate. 2. Clear PLLON to disable the PLL and select high bandwidth. 3. Select the speed using PS1 and PS0. 4. Set PLLON to enable the PLL. 5. Wait a time of 90% tPLLS for the PLL frequency to stabilize and select manual low bandwidth, wait another 10% tPLLS. 6. Set BCS to switch to the high-frequency bus rate The user cannot switch among the high speeds with the BCS bit set. Following the procedure above will prevent possible bursts of high frequency operation during the re-configuration of the PLL. Whenever the PLL is first enabled, the wide bandwidth mode should be used. This enables the PLL frequency to ramp up quickly. When the output frequency is near the desired frequency, the filter is switched to the narrow bandwidth mode to make the final frequency more stable. NON-DISCLOSURE General Release Specification Phase-Locked Loop (PLL) Synthesis For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesis Phase-Locked Loop Control Register 9.3 Phase-Locked Loop Control Register This read/write register contains the control bits which select the PLL frequency and enable/disable the synthesizer. Address: $0007 Bit 7 Read: 0 BCS 0 0 0 BWC 0 PLLON 1 VCOTST 1 PS1 0 PS0 1 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... Write: Reset: 0 Figure 9-2. Phase-Locked Loop Control Register (PLLCR) BCS -- Bus Clock Select When this bit is set, the output of the PLL is used to generate the internal processor clock. When clear, the internal bus clock is driven by the crystal (OSC1 / 2). Once BCS has been changed, it may take up to 1.5 OSC1 cycles + 1.5 PLLOUT cycles to make the transition. During the transition, the clock select output will be held low and all CPU and timer activity will cease until the transition is complete. Before setting BCS, allow at least a time of tPLLS after PLLON is set. This bit cannot be set unless the PLLON bit is already set on a previous instruction. Reset clears this bit. BWC -- Bandwidth Control This bit selects high bandwidth control when set and low bandwidth control when clear. The low bandwidth driver is always enabled, so this bit determines whether the high bandwidth driver is on or off. When the PLL is turned on, the BWC bit should be set to a logic 1 for a time of 90% tPLLS to allow the PLL time to acquire a frequency close to the desired frequency. The BWC bit should then be cleared and software should delay for a time 10% tPLLS to allow the PLL time to make the final adjustments. The PLL clock cannot be used (BCS bit set). Although it is NOT prohibited in hardware, the BCS bit should not be set unless the BWC bit is cleared and the proper delay times have been followed. The PLL will generate a lower jitter clock when the BWC bit is cleared. Reset clears this bit. MC68HC05E5 -- Rev. 1.0 Phase-Locked Loop (PLL) Synthesis For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesis REQUIRED PLLON -- PLL On This bit activates the synthesizer circuit without connecting it to the control circuit. This allows the synthesizer to stabilize before it can drive the CPU clocks. When this bit is cleared, the PLL is shut off and the BCS bit cannot be set. (Setting the BCS bit would engage the disabled PLL onto the bus.) Reset sets this bit. NOTE: PLLON cannot be cleared unless the BCS bit has been cleared on a previous write to the register. VCOTST -- VCO Test This bit is used to isolate the loop filter from the VCO to facilitate testing. When cleared only in test or self-check modes, the low bandwidth mode of the PLL filter is disabled. When set, the loop filter operates as indicated by the value of the BWC bit. Reset sets this bit. Freescale Semiconductor, Inc... AGREEMENT NOTE: This bit is intended for use by Motorola to test and characterize the PLL. This bit cannot be cleared in user mode. PS1-PS0 -- PLL Synthesizer Speed Select These two bits select one-of-four taps from the PLL to drive the CPU clocks. These bits are used in conjunction with PLLON and BCS bits in the PLL control register. These bits should not be written if BCS in the PLLCR is at a logic high. Reset clears PS1 and sets PS0, choosing a bus clock frequency of 1.049 MHz. Table 9-1. PS1 and PS0 Speed Selects with 32.768-kHz Crystal PS1-PS0 00 01 10 11 524 kHz 1.049 MHz 2.097 MHz 4.194 MHz Reset Condition See Note Below See Note Below CPU Bus Clock Frequency (fop) NON-DISCLOSURE NOTE: For the standard MC68HC05E5, the 4.194-MHz bus clock frequency should never be selected, and the 2.097-MHz bus clock frequency should not be selected when running the part below V = 4.5 V. DD General Release Specification Phase-Locked Loop (PLL) Synthesis For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesis Operation During Stop Mode 9.4 Operation During Stop Mode The PLL is switched to low-frequency bus rate and is temporarily turned off when STOP is executed. Coming out of stop mode with an external IRQ, the PLL is turned on with the same configuration it had before going into STOP, with the exception of BCS which is reset. Otherwise, the PLL control register is in the reset condition. 9.5 Noise Immunity Freescale Semiconductor, Inc... The MCU should be insulated as much as possible from noise in the system. We recommend the following steps be taken to help prevent problems due to noise injection. 1. The application environment should be designed so that the MCU is not near signal traces which switch often, such as a clock signal. 2. The oscillator circuit for the MCU should be placed as close as possible to the OSC1 and OSC2 pins on the MCU. 3. All power pins should be filtered (to minimize noise on these signals) by using bypass capacitors placed as close as possible to the MCU. See the application note Designing for Electromagnetic Compatibility (EMC) with HCMOS Microcontrollers, available through the Motorola Literature Distribution Center, Motorola document number AN1050/D. MC68HC05E5 -- Rev. 1.0 Phase-Locked Loop (PLL) Synthesis For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Phase-Locked Loop (PLL) Synthesis REQUIRED NON-DISCLOSURE General Release Specification Phase-Locked Loop (PLL) Synthesis For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 10. Computer Operating Properly (COP) Watchdog 10.1 Contents 10.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .65 System Control and Status Register. . . . . . . . . . . . . . . . . . . . .66 COP During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 COP During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .68 Freescale Semiconductor, Inc... 10.3 10.4 10.5 10.2 Introduction The COP watchdog system is a mask-programmable feature which will generate a system reset if not serviced within the specified COP timeout period. The COP counter chain is derived from an output of the CPI circuit. This input signal is divided to give the COP reset rate selected by the first write to the system control and status register (SCSR) located at address $13. A COP reset is done by writing a logic zero to bit 0 of address $1FF0. This will reset the COP counter chain and begin the timeout countdown again. The COP counter chain is also cleared when the MCU is in reset or stop mode. MC68HC05E5 -- Rev. 1.0 Computer Operating Properly (COP) Watchdog For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Computer Operating Properly (COP) Watchdog REQUIRED 10.3 System Control and Status Register The SCSR is a read/write register containing the control flags for the COP rate, COP inhibit, and IRQ level and status flags indicating the cause of the last reset. Figure 10-1 shows the value of each bit in the SCSR when coming out of reset. Address: $0013 Bit 7 6 0 0 5 0 0 4 STOPR R 3 ILADR R 2 COPR R 1 CRS1 0 Bit 0 CRS0 0 Freescale Semiconductor, Inc... AGREEMENT Read: 0 Write: Reset: 0 R = Determined by cause of previous reset Figure 10-1. System Control and Status Register (SCSR) NOTE: The debounce time for the IRQ input must be shorter than the COP timeout period. STOPR -- Illegal STOP Instruction Reset STOPR is a read-only status bit. This bit is set by the execution of a STOP instruction when the STOP instruction option is disabled. This bit is cleared by POR, external reset, or COP reset. 1 = Last reset was the execution of a disabled STOP instruction. 0 = Last reset was not the execution of a disabled STOP instruction. ILADR -- Illegal Address Reset ILADR is a read-only status bit. This bit is set by an ILADR reset, but is cleared by POR, external reset, or COP reset. 1 = Last reset was an ILADR reset. 0 = Last reset was not an ILADR reset. NON-DISCLOSURE General Release Specification Computer Operating Properly (COP) Watchdog For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Computer Operating Properly (COP) Watchdog System Control and Status Register COPR -- COP Reset COPR is a read-only status bit. This bit is set by a COP reset, but is cleared by POR, external reset, or illegal address reset. 1 = Last reset was a COP reset. 0 = Last reset was not a COP reset. NOTE: The COP watchdog reset is a mask option. Therefore, a COP reset will only occur when this option is enabled. This option cannot be disabled by software. CRS1 and CRS0 -- COP Rate Select The value of these two bits determines the COP timeout rate. These bits can be written only on the first write to this register after reset. If these bits are never written to, the COP reset rate will be set at one second. The COP counter chain is cleared when these bits are written. Freescale Semiconductor, Inc... NOTE: Although these bits default to zero, the user should write to these bits to prevent subsequent writes from changing the COP rate. A bit set/clear for any bit in this register is executed as a read-modify-write of this register. If used as the first write to this register, further writes to CRS1 and CRS0 would not be valid, and the default value would be set. Table 10-1. COP Rates at fosc = 32.768 kHz CRS1 0 0 1 1 CRS0 0 1 0 1 Minimum COP Rate 1 second 2 seconds 4 seconds 8 seconds MC68HC05E5 -- Rev. 1.0 Computer Operating Properly (COP) Watchdog For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Computer Operating Properly (COP) Watchdog REQUIRED 10.4 COP During Wait Mode The CPU clock halts during wait mode, but the oscillator and the COP system are still active. The software should exit wait mode to service the COP system before the COP timeout period. 10.5 COP During Stop Mode Prior to entry into stop mode, the COP should be cleared. This allows for proper stop recovery and eliminates a possible COP time out during stop mode recovery, if the COP was about to time out prior to the STOP instruction. If enabled, stop mode turns off the oscillator and, therefore, will stop the COP. NON-DISCLOSURE General Release Specification Computer Operating Properly (COP) Watchdog For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 11. Motorola Bus (M Bus) Interface 11.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .70 M-Bus Interface Features . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 M-Bus System Configuration . . . . . . . . . . . . . . . . . . . . . . . . . .71 Freescale Semiconductor, Inc... 11.3 11.4 11.5 M-Bus Protocol . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .71 11.5.1 Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .72 11.5.2 Slave Address Transmission. . . . . . . . . . . . . . . . . . . . . . . .73 11.5.3 Data Transfer . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .73 11.5.4 Repeated Start Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11.5.5 Stop Signal . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11.5.6 Arbitration Procedure . . . . . . . . . . . . . . . . . . . . . . . . . . . . .74 11.5.7 Clock Synchronization. . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 11.5.8 Handshaking . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .75 11.6 M-Bus Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.6.1 M-Bus Address Register . . . . . . . . . . . . . . . . . . . . . . . . . . .76 11.6.2 M-Bus Frequency Divider Register . . . . . . . . . . . . . . . . . . .78 11.6.3 M-Bus Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .80 11.6.4 M-Bus Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . .82 11.6.5 M-Bus Data I/O Register . . . . . . . . . . . . . . . . . . . . . . . . . . .84 11.7 M-Bus Pin Configuration. . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.8 Programming Considerations . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.8.1 Initialization . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .86 11.8.2 Generation of a Start Signal and the First Byte of Data Transfer . . . . . . . . . . . . . . . . . . . . . . .87 11.8.3 Software Responses after Transmission or Reception of a Byte . . . . . . . . . . . . . . . . . . . . . . . . . .88 11.8.4 Generation of the Stop Signal . . . . . . . . . . . . . . . . . . . . . . .89 11.8.5 Generation of a Repeated Start Signal . . . . . . . . . . . . . . . .90 MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.8.6 11.8.7 11.9 Slave Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Arbitration Lost . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .90 Operation During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.10 Operation During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . .91 11.2 Introduction Motorola bus (M bus) is a 2-wire, bidirectional serial bus which provides a simple, efficient way for data exchange between devices. It is fully compatible to I2C bus standards and is similar to the MC68HC05T10. This bus is suitable for applications that require frequent communications over a short distance between a number of devices. It also provides a flexibility that allows additional devices to be connected to the bus. The maximum data rate is limited to 100 Kbits and the maximum communication distance and number of devices that can be connected is limited by the maximum bus capacitance of 400 pF. The M-bus system is a true multimaster bus including collision detection and arbitration to prevent data corruption if two or more masters intend to control the bus simultaneously. This feature provides the capability for complex applications with multiprocessor control. It may also be used for rapid testing and alignment of end products by way of external connections to an assembly-line computer. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface M-Bus Interface Features 11.3 M-Bus Interface Features Features of the M-bus interface include: * * * * Fully Compatible with I2C Bus Standard Multimaster Operation Software Programmable for 1of 32 Different Serial Clock Frequencies Software Selectable Acknowledge Bit Interrupt Driven Byte-by-Byte Data Transfer Arbitration Lost Driven Interrupt with Automatic Mode Switching from Master to Slave Calling Address Identification Interrupt Generate/Detect the Start or Stop Signal Repeated Start Signal Generation Generate/Recognize the Acknowledge Bit Bus Busy Detection Freescale Semiconductor, Inc... * * * * * * * The M-bus system uses a serial data line (SDA) and a serial clock line (SCL) for data transfer. All devices connected to it must have open-drain or open-collector outputs and the logical AND function is performed on both lines by two pullup resistors. 11.5 M-Bus Protocol Normally, a standard communication is composed of four parts: start signal, slave address transmission, data transfer, and stop signal. These are described briefly in the following subsections and illustrated in Figure 11-1. MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 11.4 M-Bus System Configuration AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.5.1 Start Signal When the bus is free (for example, no master device is engaging the bus and both SCL and SDA lines are at logical high), a master may initiate communication by sending a start signal. As shown in Figure 11-1, a start signal is defined as a high-to-low transition of SDA while SCL is high. This signal denotes the beginning of new data transfer (each data transfer may contain several bytes of data) and wakes up all slaves. Freescale Semiconductor, Inc... AGREEMENT MSB SCL 1 1 0 0 0 0 1 LSB 1 ACKNOWLEDGE BIT MSB 1 1 0 0 0 0 1 LSB 1 NO ACKNOWLEDGE SDA START SIGNAL STOP SIGNAL NON-DISCLOSURE MSB SCL 1 1 0 0 0 0 1 LSB 1 ACKNOWLEDGE BIT MSB 1 1 0 0 0 0 1 LSB 1 NO ACKNOWLEDGE SDA START SIGNAL REPEATED START SIGNAL STOP SIGNAL Figure 11-1. M-Bus Transmission Signal Diagram General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface M-Bus Protocol 11.5.2 Slave Address Transmission Immediately after the start signal, the first byte of data transfer is the slave address transmitted by the master. This data is a 7-bit calling address followed by a R/W bit. The R/W bit tells the slave the desired direction of data transfer. Only the slave with a matched address will respond by sending back an acknowledge bit. This acknowledge bit is accomplished by pulling SDA low on the ninth clock cycle. (See Figure 11-1.) Freescale Semiconductor, Inc... 11.5.3 Data Transfer Once a successful slave addressing is achieved, the data transfer can proceed byte by byte in the direction specified by the R/W bit sent by the calling master. Each data byte is eight bits long. Data can be changed only when SCL is low and must be held stable while SCL is high as shown in Figure 11-1. The MSB is transmitted first and each byte has to be followed by an acknowledge bit. The acknowledge bit is signalled by the receiving device by pulling the SDA low on the ninth clock cycle. Therefore, one complete data byte transfer needs nine clock cycles. If the slave receiver does not acknowledge the master, the SDA line should be left high by the slave. The master can then generate a stop signal to abort the data transfer or a start signal (repeated start) to commence a new transfer. If the master receiver does not acknowledge the slave transmitter after a byte has been transmitted, it means an "end of data" to the slave. The slave should now release the SDA line for the master to generate a stop or start signal. MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.5.4 Repeated Start Signal As shown in Figure 11-1, a repeated start signal is used to generate a start signal without first generating a stop signal to terminate the communication. This is used by the master to communicate with another slave or with the same slave in a different mode (transmit/receive mode) without releasing the bus. 11.5.5 Stop Signal Freescale Semiconductor, Inc... AGREEMENT The master can terminate the communication by generating a stop signal to free the bus. However, the master may generate a start signal followed by a calling command without first generating a stop signal. This is called repeat start. A stop signal is defined as a low-to-high transition of SDA while SCL is at logical high. (See Figure 11-1.) 11.5.6 Arbitration Procedure This interface circuit is a true multimaster system which allows more than one master to be connected to it. If two or more masters try to control the bus at the same time, a clock synchronization procedure determines the bus clock, for which the low period is equal to the longest clock low period and the high is equal to the shortest one among the masters. A data arbitration procedure determines the priority. The masters will lose arbitration if they transmit a logic 1 while another transmits logic 0. The losing masters will immediately switch over to slave receive mode and stop its data and clock outputs. In this case, the transition from master to slave mode will not generate a stop condition; however, a software bit will be set by hardware to indicate loss of arbitration. NON-DISCLOSURE General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface M-Bus Protocol 11.5.7 Clock Synchronization Since wired-AND logic is performed on the SCL line, a high-to-low transition will affect the devices connected to the bus. The devices start counting their low period and once a device's clock has gone low, it will hold the SCL line low until the clock high state is reached. However, the change of low to high in this device clock may not change the state of the SCL line if another device clock is still within its low period. Therefore, the synchronized clock SCL will be held low by the device with the longest low period. Devices with shorter low periods enter a high wait state during this time. (See Figure 11-2.) When all devices concerned have counted off their low period, the synchronized SCL line will be released and go high. There will then be no difference between the device clocks and the state of the SCL line and all devices will start counting their high periods. The first device to complete its high period will again pull the SCL line low. Freescale Semiconductor, Inc... 11.5.8 Handshaking The clock synchronization mechanism can be used as a handshake in data transfer. Slave devices may hold the SCL low after completion of one byte. In such cases, the device will halt the bus clock and force the master clock into a wait state until the slave releases the SCL line. START COUNTING HIGH PERIOD WAIT SCL1 SCL2 SCL INTERNAL COUNTER RESET Figure 11-2. Clock Synchronization MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.6 M-Bus Registers Five different registers are used in the M-bus interface. The internal configuration of these registers is discussed in the following paragraphs. NOTE: The register addresses show only the low-order address bits (for example ABL3-ABL0). The registers can be placed anywhere in the device memory map by generating an appropriate module select signal in the map logic. A block diagram of the M-bus system is shown in Figure 11-3. Freescale Semiconductor, Inc... AGREEMENT 11.6.1 M-Bus Address Register Address: $0018 Bit 7 Read: MAD7 Write: Reset: 0 0 0 0 0 0 0 -- MAD6 MAD5 MAD4 MAD3 MAD2 MAD1 6 5 4 3 2 1 Bit 0 = Unimplemented NON-DISCLOSURE Figure 11-3. M-Bus Address Register (MADR) Bit 1-Bit 7 Each of these bits contains its own specific slave address. This register is cleared upon reset. General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc... DATA BUS CONTROL REGISTER STATUS REGISTER MC68HC05E5 -- Rev. 1.0 M I E N M S T A M T X M B B FREQUENCY DIVIDER REGISTER S R W M I F M C F M A L ADDRESS REGISTER T X A K M A A S R X A K ADDRESS COMPARATOR M-BUS INTERRUPT SCL CONTROL M-BUS CLOCK GENERATOR SYNC LOGIC TRANSMITTER SHIFT REGISTER RECEIVER SHIFT REGISTER START, STOP DETECTOR & ARBITRATION START, STOP GENERATOR & TIMING SYNC TRANSMITTER CONTROL RECEIVER CONTROL SDA CONTROL M E N INTERRUPT Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com SCL SDA Motorola Bus (M Bus) Interface M-Bus Registers General Release Specification Figure 11-4. M-Bus Interface Block Diagram NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.6.2 M-Bus Frequency Divider Register Address: $0019 Bit 7 6 5 4 FD4 3 FD3 0 2 FD2 0 1 FD1 0 Bit 0 FD0 0 Read: Write: Reset: -- -- -- 0 Freescale Semiconductor, Inc... AGREEMENT = Unimplemented Figure 11-5. M-Bus Frequency Divider Register (MFDR) Bit 0-Bit 4 These bits are used for clock rate selection. The serial bit clock frequency is equal to the CPU clock divided by the divider shown in Table 11-1. This register is cleared upon reset. For a 4-MHz external crystal operation (2-MHz internal operating frequency), the serial bit clock frequency of the M-bus ranges from 460 Hz to 90,909 Hz. NON-DISCLOSURE General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface M-Bus Registers Table 11-1. M-Bus Clock Prescaler FD4, FD3, FD2, FD1, FD0 00000 00001 00010 00011 00100 Divider 22 24 28 34 44 48 56 68 88 96 112 136 176 192 224 272 FD4, FD3, FD2, FD1, FD0 10000 10001 10010 10011 10100 10101 10110 10111 11000 11001 11010 11011 11100 11101 11110 11111 Divider 352 384 448 544 704 768 896 1088 1408 1536 1792 2176 2816 3072 3584 4352 Freescale Semiconductor, Inc... 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.6.3 M-Bus Control Register The M-bus control register (MCR) provides five control bits and is cleared upon reset. Address: $001A Bit 7 Read: MEN MIEN 0 MSTA 0 MTX 0 TXAK 0 MMUX 0 -- -- Write: Reset: 0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... AGREEMENT = Unimplemented Figure 11-6. M-Bus Control Register (MCR) MEN -- M-Bus Enable Bit If MEN is set, the M-bus interface system is enabled. If MEN is cleared, the interface is reset and disabled. The MEN bit must be set first before any bits of MCR are set. MIEN -- M-Bus Interrupt Enable Bit If MIEN is set, an interrupt occurs provided the MIF flag in the status register is set and the I bit in the condition code register is cleared. If MIEN is cleared, the M-bus interrupt is disabled. MSTA -- Master/Slave Mode Select Bit Upon reset, this bit is cleared. When this bit is changed from a logic 0 to a logic 1, a start signal is generated on the bus, and master mode is selected. When this bit is changed from a logic 1 to a logic 0, a stop signal is generated and the operating mode changes from master to slave. In master mode, a bit clear immediately followed by a bit set generates a repeated start signal (see Figure 11-1) without generating a stop signal. 1 = Master 0 = Slave NON-DISCLOSURE General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface M-Bus Registers MTX -- Transmit/Receiver Mode Select Bit This bit selects the direction of master and slave transfers. When addressed as a slave, this bit should be set by software according to the SRW bit in the status register. In master mode, this bit should be set according to the type of transfer required. Hence, for address cycles this bit will always be high. 1 = Transmit 0 = Receive Freescale Semiconductor, Inc... TXAK -- Transmit Acknowledge Enable Bit If TXAK is cleared, an acknowledge signal will be sent out to the bus at the ninth clock bit after receiving one byte of data. When TXAK is set, there will be no acknowledge signal response (for example, acknowledge bit = 1). MMUX -- M-Bus Multiplexer This bit is used to enable PB7 and PB6 to be under the control of the M-bus circuit. When set, both PB7 and PB6 become open-collector outputs or inputs when enabled by the M-bus control. When cleared PB7 and PB6 are under control of the port DDR logic. This bit can be set or cleared independent of the MEN bit. Caution should be used if PB7 and PB6 are used as general-purpose I/O. 1 = M-bus control 0 = POR condition, port B DDR control MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.6.4 M-Bus Status Register This status register is software readable only with exception of bit 1 (MIF) and bit 4 (MAL) which are software clearable. All bits are cleared upon reset except bit 7 (MCF) and bit 0 (RXAK). Address: $001B Bit 7 Read: MCF 6 MAAS 5 MBB 4 MAL MAL CLR 1 0 0 0 -- 0 3 2 SRW 1 MIF MIF CLR 0 1 Bit 0 RXAK Freescale Semiconductor, Inc... AGREEMENT Write: Reset: = Unimplemented Figure 11-7. M-Bus Status Register (MSR) MCF -- Data Transferring Bit While one byte of data is being transferred, this bit is cleared. It is set by the falling edge of the ninth clock of a byte transfer. 1 = Transfer complete 0 = Transfer in progress MAAS -- Addressed as a Slave Bit When its own specific address (MADR) is matched with the calling address, this bit is set. The CPU is interrupted provided MIEN is set. Then CPU needs to check the SRW bit and set its TX/RX mode accordingly. 1 = Addressed as a slave 0 = Not addressed Writing to the M-bus control register clears this bit. MBB -- Bus Busy Bit This bit indicates the status of the bus. When a start signal is detected, the MBB is set. If a stop signal is detected, it is cleared. 1 = Bus busy 0 = Bus idle NON-DISCLOSURE General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface M-Bus Registers MAL -- Arbitration Lost Bit MAL is set by hardware when the arbitration procedure is lost during a master transmission. This bit must be cleared by software. SRW -- R/W Command Bit When MAAS is set, the R/W command bit of the calling address (sent from master) is latched into the R/W command bit (SRW). Checking this bit, the CPU can select the slave transmit/receive mode according to the command of master. 1 = Slave transmit, master reading from slave 0 = Slave receive, master writing to slave MIF -- M-Bus Interrupt Bit MIF is set when an interrupt is pending. This will cause an M-bus interrupt request provided MIEN is set. This bit is set when one of the following events occurs: - Transmission of one byte is completed. The bit is set at the falling edge of the ninth clock. - Reception of a calling address which matches its own specific address in slave receive mode. - Arbitration is lost. This bit must be cleared by writing a logic 0 to it. RXAK -- Receive Acknowledge Bit If RXAK is low, it indicates an acknowledge signal has been received after the completion of an 8-bit data transmission on the bus. If RXAK is high, it means no acknowledge signal is detected at the ninth clock. 1 = No acknowledge received 0 = Acknowledge received RXAK is set upon reset. Freescale Semiconductor, Inc... MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.6.5 M-Bus Data I/O Register Address: $001C Bit 7 6 MD6 5 MD5 4 MD4 3 MD3 2 MD2 1 MD1 Bit 0 MD0 Read: MD7 Write: Reset: Freescale Semiconductor, Inc... AGREEMENT Unaffected by Reset Figure 11-8. M-Bus Data I/O Register (MDR) In master transmit mode, data written to this register is sent (MSB first) to the bus automatically. In master receive mode, reading from this register initiates reception of the next byte of data. This is accomplished by holding the SCL clock line low until a read of this register occurs. Once the data is read, the device releases the SCL line to allow the transmitting device to transmit the next byte. In slave mode, the same function is available after it is addressed. NON-DISCLOSURE General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface M-Bus Registers CLEAR MIF Y MASTER MODE N TX TX/RX Y RX Y ARBITRATION LOST N LAST BYTE TRANSMITTED LAST BYTE TO BE READ N Y CLEAR MAL Y MAAS = 1 N RX Freescale Semiconductor, Inc... MAAS = 1 Y RXAK=0 Y WRITE NEXT BYTE TO MDR N LAST 2nd BYTE TO BE READ N SET TXAK = 1 GENERATE STOP SIGNAL SET TX MODE Y (READ) TX/RX SRW = 1 N (WRITE) TX READ MDR AND STORE GENERATE STOP SIGNAL WRITE TO MDR Y ACK FROM RECEIVER N SWITCH TO RX MODE DUMMY READ FROM MDR TX NEXT BYTE SET RX MODE READ DATA FROM MDR AND STORE DUMMY READ FROM MDR RTI Figure 11-9. Flowchart of M-Bus Interrupt Routine MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT N N REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.7 M-Bus Pin Configuration When the M-bus interface is enabled with the MEN bit and the MMUX bit in the M-bus control register (MCR), the port B data direction register bits 6 and 7 relinquish control to the M-bus control register bits. Enabling the M-bus does not alter the state of the port B DDR bits. 11.8 Programming Considerations AGREEMENT Freescale Semiconductor, Inc... Programming considerations are discussed in the following subsections. 11.8.1 Initialization Initialization is accomplished using the following steps: 1. Update frequency divider register (MFDR) to select an SCL frequency. 2. Update M-bus address register (MADR) to define its own slave address. 3. Set MEN bit of the M-bus control register (MCR) to enable the M-bus interface system and set the MMUX bit to allow M-bus control of the PB7 and PB6 pins. 4. Modify the M-bus control register (MCR) bits to select master/slave mode, transmit/receive mode, interrupt enable, or not. NON-DISCLOSURE General Release Specification MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface Programming Considerations 11.8.2 Generation of a Start Signal and the First Byte of Data Transfer After completion of the initialization procedure, serial data can be transmitted by selecting the master transmitter mode. If the device is connected to a multimaster bus system, the state of the M-bus busy bit (MBB) must be tested to check whether the serial bus is free. If the bus is free (MBB = 0), the start condition and the first byte (the slave address) can be sent. An example of a program which generates the start signal and transmits the first byte of data (slave address) is shown here. (The MMUX bit must be set to allow control of PB7 and PB6 pins.) CHFALG SEI BRSET ; 5,MSR,CHFLAG; ; ; 4,MCR ; 5,MCR ; ; #CALLING ; MDR ; ; ; DISABLE INTERRUPT CHECK THE MBB BIT OF THE STATUS REGISTER. IF IT IS SET, WAIT UNTIL IT IS CLEAR SET TRANSMIT MODE SET MASTER MODE i.e., GENERATE START CONDITION GET THE CALLING ADDRESS TRANSMIT THE CALLING ADDRESS ENABLE INTERRUPT Freescale Semiconductor, Inc... TXSTART BSET BSET LDA STA CLI MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.8.3 Software Responses after Transmission or Reception of a Byte Transmission or reception of a byte will set the data transferring bit (MCF) to a logic 1, which indicates one byte of communication is finished. Also, the M-bus interrupt bit (MIF) is set to generate an M-bus interrupt if the interrupt function is enabled during initialization. Software must clear the MIF bit in the interrupt routine first. The MCF bit will be cleared by reading from the M-bus data I/O register (MDR) in receive mode or writing to MDR in transmit mode. Software may serve the M-bus I/O in the main program by monitoring the MIF bit if the interrupt function is disabled. The following is an example of a software response by a master transmitter in the interrupt routine. See Figure 11-9. ISR BCLR BRCLR BRCLR BRSET 1,MSR 5,MCR,SLAVE 4,MCR,RECEIVE 0,MSR,END ; ; ; ; ; ; ; ; ; ; CLEAR THE MIF FLAG CHECK THE MSTA FLAG, BRANCH IF SLAVE MODE CHECK THE MODE FLAG, BRANCH IF IN RECEIVE MODE CHECK ACK FROM RECEIVER IF NO ACK, END OF TRANSMISSION GET THE NEXT BYTE OF DATA TRANSMIT THE DATA Freescale Semiconductor, Inc... AGREEMENT TRANSMIT LDA STA DATABUF MDR NON-DISCLOSURE General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface Programming Considerations 11.8.4 Generation of the Stop Signal A data transfer ends with a stop signal generated by the master device. A master transmitter can simply generate a stop signal after all the data has been transmitted. The following is an example showing how a stop condition is generated by a master transmitter. MASTX BRSET LDA BEQ LDA STA DEC BRA BCLR RTI 0,MSR,END TXCNT END DATABUF MDR TXCNT EMASTX 5,MCR ; ; ; ; ; ; ; ; ; ; ; IF NO ACK, BRANCH TO END GET VALUE FROM THE TRANSMITTING COUNTER IF NO MORE DATA, BRANCH TO END GET NEXT BYTE OF DATA TRANSMIT THE DATA DECREASE THE TXCNT EXIT GENERATE A STOP CONDITION RETURN FROM INTERRUPT Freescale Semiconductor, Inc... END EMASTX If a master receiver wants to terminate a data transfer, it must inform the slave transmitter by not acknowledging the last byte of data. This can be done by setting the transmit acknowledge bit (TXAK) before reading the second to the last byte of data. Before reading the last byte of data, a stop signal must be generated first. The following is an example showing how a stop signal is generated by a master receiver. MASR DEC BEQ LDA DECA BNE BSET BRA BCLR LDA STA RTI RXCNT ENMASR RXCNT NXMAR 3,MCR NXMAR 5,MCR MDR RXBUF ; LAST BYTE TO BE READ ; ; ; ; CHECK LAST 2ND BYTE TO BE READ NOT LAST ONE OR LAST SECOND LAST SECOND, DISABLE ACK TRANSMITTING LAMAR ENMASR NXMAR ; LAST ONE, GENERATE 'STOP' ; SIGNAL ; READ DATA AND STORE MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED 11.8.5 Generation of a Repeated Start Signal If at the end of data transfer the master still wants to communicate on the bus, it can generate another start signal followed by another slave address without first generating a stop signal. A program example is shown here. RESTART BCLR BSET LDA STA 5,MCR 5,MCR #CALLING MDR ; ; ; ; ; ; ANOTHER START (RESTART) IS GENERATED BY THESE TWO CONSEQUENCE INSTRUCTION GET THE CALLING ADDRESS TRANSMIT THE CALLING ADDRESS Freescale Semiconductor, Inc... AGREEMENT 11.8.6 Slave Mode In the slave service routine, the master addressed as slave bit (MAAS) should be tested to see if a calling of its own address has just been received. If MAAS is set, software should set the transmit/receive mode select bit (MTX bit of MCR) according to the R/W command bit (SRW). Writing to the MCR clears the MAAS automatically. A data transfer may then be initiated by writing information to MDR or dummy reading from MDR. In the slave transmitter routine, the received acknowledge bit (RXAK) must be tested before transmitting the next byte of data. If RXAK is set, indicating an end of the data signal from the master receiver, then RXAK must switch from transmitter mode to receiver mode by software. A dummy read must follow to release the SCL line so that the master can generate a stop signal. NON-DISCLOSURE 11.8.7 Arbitration Lost If more than one master wants to engage the bus simultaneously, only one master wins and the others lose arbitration. The arbitration loss devices immediately switch to slave receive mode by hardware. Their data output to the SDA line is stopped, but the internal transmitting clock still runs until the end of the current byte transmission. An interrupt occurs when this dummy byte transmission is accomplished with General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface Operation During Wait Mode MAL = 1 and MSTA = 0. If one master attempts to start transmission while the bus is being engaged by another master: 1. The hardware will inhibit the transmission. 2. The MSTA bit will switch from one to zero without generating a stop condition. 3. Interrupt to CPU will be generated. 4. MAL will be set to indicate that the attempt to engage the bus has failed. Freescale Semiconductor, Inc... In consideration of these cases, the slave service routine should test the MAL first, and software should clear the MAL bit if it is set. 11.9 Operation During Wait Mode During wait mode the M-bus block is idle. If in slave mode, the M-bus block will wake up on receiving a valid start condition. If the interrupt is enabled, the CPU will come out of wait mode after the end of a byte transmission. In stop mode, the whole block is disabled. MC68HC05E5 -- Rev. 1.0 Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 11.10 Operation During Stop Mode AGREEMENT REQUIRED Freescale Semiconductor, Inc. Motorola Bus (M Bus) Interface REQUIRED NON-DISCLOSURE General Release Specification Motorola Bus (M Bus) Interface For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 12. Synchronous Serial Interface (SSI) 12.1 Contents 12.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .94 Freescale Semiconductor, Inc... 12.3 SSI Signals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.1 Serial Clock (SCK) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .96 12.3.2 Serial Data Input/Output (SDIO) . . . . . . . . . . . . . . . . . . . . .96 12.4 SSI Registers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.4.1 SSI Control Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .98 12.4.2 SSI Status Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .101 12.4.3 SSI Data Register . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 12.5 12.6 12.7 SSI During Stop Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .102 SSI During Wait Mode . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 SSI Pin Configuration . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .103 MC68HC05E5 -- Rev. 1.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED 12.2 Introduction This synchronous serial I/O module is also used on the MC68HC05X1. The module is similar to the SIOP used on the MC68HC05P7 and the MC68HC705P9 and the SPI used on the MC68HC05L5. The SSI is a 2-wire master/slave system including serial clock (SCK) and serial data input output (SDIO). Data is transferred eight bits at a time. An interrupt may be generated at the completion of each transfer, and a software programmable option determines whether the SSI transfers data most significant bit (MSB) or least significant bit (LSB) first. When operating as a master device, the serial clock speed is selectable between four rates; as a slave device, the clock speed may be chosen over a wide range. Refer to Figure 12-1. In master mode, transmission is initiated by a write to the SSI data register (SDR). A transfer cannot be initiated in slave mode; however, the external master will initiate the transfer. The programmer must choose between master or slave mode before the SSI is enabled. It is up to the programmer to ensure that only one master exists in the system at any one time. All devices in the system must operate with the same clock polarity and data rates. Slaves should always be disabled before the master is disabled. Likewise, the master should always be enabled before the slaves are enabled. NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) Introduction INTERNAL BUS CONTROLS/ADDRESS BUS DATA BUS INTERRUPT CIRCUIT CONTROL LOGIC TO INTERRUPT LOGIC 00000 SSI STATUS REGISTER START SSI CONTROL REGISTER MSTR CPOL SSI DATA REGISTER LSBF SR HFF SDIO Freescale Semiconductor, Inc... SE CLOCK GENERATOR SCK PB3/TIPL MSTR & Figure 12-1. SSI Block Diagram MC68HC05E5 -- Rev. 1.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT SF DCOL SE REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED 12.3 SSI Signals The following sections describe the SSI signals. 12.3.1 Serial Clock (SCK) In master mode (MSTR = 1), the SCK pin is an output with a selectable frequency of: fop divided by 16 (SR1-SR0 = 00), fop divided by 8 (SR1-SR0 = 01), fop divided by 4 (SR1-SR0 = 10), or fop divided by 2 (SR1-SR0 = 11). This pin will be high (CPOL = 1) or low (CPOL = 0) between transmissions. In slave mode (MSTR = 0), the SCK pin is an input and the clock must be supplied by an external master with a maximum frequency of fop divided by 2. There is no minimum SCK frequency. This pin should be driven high (CPOL = 1) or low (CPOL = 0) between transmissions by the external master and must be stable before the SSI is first enabled (SE = 1). NON-DISCLOSURE Freescale Semiconductor, Inc... AGREEMENT NOTE: Data is always captured with the SDIO pin on the rising edge of SCK. Data is always shifted out and presented at the SDIO pin on the falling edge of SCK. 12.3.2 Serial Data Input/Output (SDIO) This pin receives and transmits data to or from the SSI module as described in the following paragraphs. SDIO as an Output Pin Prior to enabling the SSI (SE = 0), the SDIO pin will be three-stated. The SDIO pin will be active when the SSI is enabled (SE = 1), the serial direction (SDIR = 1) bit is set, and MSTR = 1. The state of the General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) SSI Signals pin will depend on the value of the CPOL bit. Data can be sent or received in either MSB first format (LSBF = 0) or LSB first format (LSBF = 1). If (CPOL = 1), the first falling edge of SCK will shift the first data bit out to the SDIO pin. Subsequent falling edges of SCK will shift the remaining data bits out. If (CPOL = 0), the first data bit will be driven out to the SDIO pin before the first rising edge of SCK. Subsequent falling edges of SCK will shift the remaining data bits out. Freescale Semiconductor, Inc... SDIO as an Input Pin The SDIO pin will accept data once the SSI is enabled and the SDIR bit = 0. Valid data must be present at least 100 ns before the rising edge of the clock and remain valid for 100 ns after the edge. See Figure 12-2 and Figure 12-3. SCK SDIO BIT 1 BIT 2 BIT 3 BIT 7 BIT 8 Figure 12-2. Synchronous Serial Interface Timing (CPOL = 1) SCK BIT 1 BIT 2 BIT 3 BIT 7 BIT 8 SDIO SE Figure 12-3. Synchronous Serial Interface Timing (CPOL = 0) MC68HC05E5 -- Rev. 1.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE SE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED 12.4 SSI Registers The SSI registers are described in the following subsections. 12.4.1 SSI Control Register This register is located at address $000A. A reset clears all of these bits, except bit 3 which is set. Writes to this register during a transfer should be avoided, with the exception of clearing the SE bit to disable the SSI. In addition, the clock polarity, rate, data format, and master/slave selection should not be changed while the SSI is enabled (SE = 1) or being enabled. Always disable the SSI, by clearing the SE bit, before altering control bits within the SCR. Address: $000A Bit 7 Read: SIE Write: Reset: 0 0 0 0 1 0 0 0 SE LSBF MSTR CPOL SDIR SR1 SR0 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... AGREEMENT NON-DISCLOSURE Figure 12-4. SSI Control Register (SCR) SIE -- SSI Interrupt Enable This bit determines whether an interrupt request should be generated when a transfer is complete. Reset clears this bit. 1 = An interrupt request will be made if the CPU is in the run or wait mode of operation and the status flag bit SF is set. 0 = No interrupt requests will be made by the SSI. SE -- SSI Enable When this bit is set, it enables the SSI and SCK pins. When this bit is cleared, any transmission in progress is aborted and the SCK and SDIO are three-stated. The SE bit is readable and writable any time. Clearing SE while a data transfer is occurring will abort the transmission and reset the bit counter. Reset clears this bit. 1 = Enable the SSI module. 0 = Disable the SSI module. General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) SSI Registers LSBF -- Least Significant Bit First The LSBF bit determines the format of the data transfer. The two formats are least significant bit (LSB) or most significant bit (MSB) transferred or received first. Reset clears this bit, initializing the SSI to MSB first order. 1 = Data will be sent and received in an LSB first format. 0 = Data will be sent and received in an MSB first format. MSTR -- Master Mode Freescale Semiconductor, Inc... CPOL -- Clock Polarity The clock polarity bit controls the state of the SCK pin between transmissions. 1 = SCK will be high between transmissions. 0 = SCK will be low between transmissions. In both cases, the data is latched on the rising edge of SCK for serial input and is valid on the rising edge of SCK for serial output. Reset sets this bit. SDIR -- Serial Data Direction When the SE bit = 1, SDIR functions as the output driver enable bit for the SDIO pin with SSI in master or in slave mode. This bit has no effect on the SDIO pin when the SSI is disabled (SE = 0). This bit is cleared by reset. 1 = Enable the output driver of the SDIO pin. 0 = Disable the output driver of the SDIO pin. MC68HC05E5 -- Rev. 1.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT Reset clears this bit and configures the SSI for slave operation. MSTR may be set at any time regardless of the state of SE. 1 = SSI is configured for master mode. The transmission is initiated by a write to the data register and the SCK pin becomes an output providing a synchronous data clock at a rate determined by the SR bit. 0 = SSI is configured to slave mode. Any transmission in progress is aborted. Transfers are initiated by an external master which should supply the clock signal to the SCK pin. REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED SR1 and SR0 -- SSI Clock Rate Select These bits determine the frequency of SCK when in master mode (MSTR = 1). They have no effect in slave mode (MSTR = 0). Table 12-1. Master Mode SCK Frequency Select SR1 0 SR0 0 1 0 1 SCK Frequency fop / 16 fop / 8 fop / 4 fop / 2 Freescale Semiconductor, Inc... AGREEMENT 0 1 1 NON-DISCLOSURE General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) SSI Registers 12.4.2 SSI Status Register The SSI status register (SSR) is located at address $000B and contains three bits. Address: $000B Bit 7 Read: SF Write: 6 DCOL 0 0 0 0 0 0 1 0 0 0 0 TIPL 0 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... = Unimplemented Figure 12-5. SSI Status Register (SSR) SF -- SSI Flag This bit is set upon occurrence of the last rising clock edge and indicates that a data transfer has taken place. It has no effect on any further transmissions and can be ignored without problem. However, SF must be cleared before a master can initiate a transfer. SF is cleared by reading the SSR with SF set followed by a read or write of the serial data register. If it is cleared before the last edge of the next byte, it will be set again. Reset clears this bit. DCOL -- Data Collision This is a read-only status bit which indicates that an invalid access to the data register has been made. This can occur any time after the first falling edge of SCK and before SF is set. DCOL is cleared by reading the status register with SF set followed by a read or write of the data register. If the last part of the clearing sequence is done after another transmission has been started, DCOL will be set again. Reset also clears this bit. TIPL The state of the PB3 pin is latched and placed into this bit on the eighth rising SCK clock during a shift operation. This is the case regardless of the state of MSTR and CPOL in the SSI control register. Reset clears this bit. MC68HC05E5 -- Rev. 1.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT Reset: 0 REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED 12.4.3 SSI Data Register This register is located at address $000C and is both the transmit and receive data register. This system is not double buffered but writes to this register during transfers are masked and will not destroy the previous contents. The SDR can be read at any time, but, if a transfer is in progress the results may be ambiguous. This register should only be written to when the SSI is enabled (SE = 1). Address: $000C Bit 7 Read: Write: Reset: Reset Results Unknown 6 5 4 3 2 1 Bit 0 Freescale Semiconductor, Inc... AGREEMENT Figure 12-6. SSI Data Register (SDR) 12.5 SSI During Stop Mode In stop mode, the SSI halts operation. The SDIO and SCK pins will maintain their states. If the SSI was nearing completion of a transfer when the stop mode is entered, it might be possible for the SSI to generate an interrupt request and cause the processor to immediately exit stop mode. To prevent this occurrence, the programmer should ensure that all transfers are complete before entering stop mode. If the SSI is configured to slave mode, then further care should be taken in entering stop mode. In slave mode, the SCK pin will still accept a clock from an external master, allowing potentially unwanted transfers to take place and power consumption to be increased. Note that the SSI will not generate interrupt requests in this situation. However, on exiting stop mode through some other means, the SF flag may be found to be set. If, at this point, SIE is also set, an interrupt request will be generated. NON-DISCLOSURE NOTE: To avoid these potential problems, it is safer to disable the SSI completely (SE = 0) before entering stop mode. General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) SSI During Wait Mode 12.6 SSI During Wait Mode The CPU clock halts during wait mode, but the SSI remains active. If interrupts are enabled, an SSI interrupt will cause the processor to exit wait mode. 12.7 SSI Pin Configuration Freescale Semiconductor, Inc... MC68HC05E5 -- Rev. 1.0 Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT When the SSI is enabled via the SE bit of the SCR ($0A), the port B data direction register bits 3-5 relinquish control to the SSI as directed by the combination of the SE, MSTR, and SDIR bits. The states of the port B DDR bits are not altered by the SSI. REQUIRED Freescale Semiconductor, Inc. Synchronous Serial Interface (SSI) REQUIRED NON-DISCLOSURE General Release Specification Synchronous Serial Interface (SSI) For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 13. Instruction Set 13.1 Contents 11.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 Freescale Semiconductor, Inc... 11.3 Addressing Modes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .106 11.3.1 Inherent . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 11.3.2 Immediate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 11.3.3 Direct . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 11.3.4 Extended . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .107 11.3.5 Indexed, No Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 11.3.6 Indexed, 8-Bit Offset . . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 11.3.7 Indexed,16-Bit Offset. . . . . . . . . . . . . . . . . . . . . . . . . . . . .108 11.3.8 Relative . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 11.4 Instruction Types . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .109 11.4.1 Register/Memory Instructions . . . . . . . . . . . . . . . . . . . . . .110 11.4.2 Read-Modify-Write Instructions . . . . . . . . . . . . . . . . . . . . .111 11.4.3 Jump/Branch Instructions . . . . . . . . . . . . . . . . . . . . . . . . .112 11.4.4 Bit Manipulation Instructions . . . . . . . . . . . . . . . . . . . . . . .114 11.4.5 Control Instructions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .115 11.5 Instruction Set Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . .116 MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 13.2 Introduction The MCU instruction set has 62 instructions and uses eight addressing modes. The instructions include all those of the M146805 CMOS Family plus one more: the unsigned multiply (MUL) instruction. The MUL instruction allows unsigned multiplication of the contents of the accumulator (A) and the index register (X). The high-order product is stored in the index register, and the low-order product is stored in the accumulator. Freescale Semiconductor, Inc... AGREEMENT 13.3 Addressing Modes The CPU uses eight addressing modes for flexibility in accessing data. The addressing modes provide eight different ways for the CPU to find the data required to execute an instruction. The eight addressing modes are: * * * * * * * * Inherent Immediate Direct Extended Indexed, no offset Indexed, 8-bit offset Indexed, 16-bit offset Relative NON-DISCLOSURE General Release Specification MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Instruction Set Addressing Modes 13.3.1 Inherent Inherent instructions are those that have no operand, such as return from interrupt (RTI) and stop (STOP). Some of the inherent instructions act on data in the CPU registers, such as set carry flag (SEC) and increment accumulator (INCA). Inherent instructions require no operand address and are one byte long. 13.3.2 Immediate Freescale Semiconductor, Inc... Immediate instructions are those that contain a value to be used in an operation with the value in the accumulator or index register. Immediate instructions require no operand address and are two bytes long. The opcode is the first byte, and the immediate data value is the second byte. 13.3.3 Direct Direct instructions can access any of the first 256 memory locations with two bytes. The first byte is the opcode, and the second is the low byte of the operand address. In direct addressing, the CPU automatically uses $00 as the high byte of the operand address. 13.3.4 Extended Extended instructions use three bytes and can access any address in memory. The first byte is the opcode; the second and third bytes are the high and low bytes of the operand address. When using the Motorola assembler, the programmer does not need to specify whether an instruction is direct or extended. The assembler automatically selects the shortest form of the instruction. MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 13.3.5 Indexed, No Offset Indexed instructions with no offset are 1-byte instructions that can access data with variable addresses within the first 256 memory locations. The index register contains the low byte of the effective address of the operand. The CPU automatically uses $00 as the high byte, so these instructions can address locations $0000-$00FF. Indexed, no offset instructions are often used to move a pointer through a table or to hold the address of a frequently used RAM or I/O location. Freescale Semiconductor, Inc... AGREEMENT 13.3.6 Indexed, 8-Bit Offset Indexed, 8-bit offset instructions are 2-byte instructions that can access data with variable addresses within the first 511 memory locations. The CPU adds the unsigned byte in the index register to the unsigned byte following the opcode. The sum is the effective address of the operand. These instructions can access locations $0000-$01FE. Indexed 8-bit offset instructions are useful for selecting the kth element in an n-element table. The table can begin anywhere within the first 256 memory locations and could extend as far as location 510 ($01FE). The k value is typically in the index register, and the address of the beginning of the table is in the byte following the opcode. NON-DISCLOSURE 13.3.7 Indexed,16-Bit Offset Indexed, 16-bit offset instructions are 3-byte instructions that can access data with variable addresses at any location in memory. The CPU adds the unsigned byte in the index register to the two unsigned bytes following the opcode. The sum is the effective address of the operand. The first byte after the opcode is the high byte of the 16-bit offset; the second byte is the low byte of the offset. Indexed, 16-bit offset instructions are useful for selecting the kth element in an n-element table anywhere in memory. As with direct and extended addressing, the Motorola assembler determines the shortest form of indexed addressing. General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Instruction Set Instruction Types 13.3.8 Relative Relative addressing is only for branch instructions. If the branch condition is true, the CPU finds the effective branch destination by adding the signed byte following the opcode to the contents of the program counter. If the branch condition is not true, the CPU goes to the next instruction. The offset is a signed, two's complement byte that gives a branching range of -128 to +127 bytes from the address of the next location after the branch instruction. Freescale Semiconductor, Inc... 13.4 Instruction Types The MCU instructions fall into the following five categories: * * * * * Register/Memory Instructions Read-Modify-Write Instructions Jump/Branch Instructions Bit Manipulation Instructions Control Instructions MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT When using the Motorola assembler, the programmer does not need to calculate the offset, because the assembler determines the proper offset and verifies that it is within the span of the branch. REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 13.4.1 Register/Memory Instructions These instructions operate on CPU registers and memory locations. Most of them use two operands. One operand is in either the accumulator or the index register. The CPU finds the other operand in memory. Table 13-1. Register/Memory Instructions Instruction Mnemonic ADC ADD AND BIT CMP CPX EOR LDA LDX MUL ORA SBC STA STX SUB AGREEMENT Freescale Semiconductor, Inc... Add Memory Byte and Carry Bit to Accumulator Add Memory Byte to Accumulator AND Memory Byte with Accumulator Bit Test Accumulator Compare Accumulator Compare Index Register with Memory Byte EXCLUSIVE OR Accumulator with Memory Byte Load Accumulator with Memory Byte Load Index Register with Memory Byte Multiply OR Accumulator with Memory Byte Subtract Memory Byte and Carry Bit from Accumulator Store Accumulator in Memory Store Index Register in Memory Subtract Memory Byte from Accumulator NON-DISCLOSURE General Release Specification MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Instruction Set Instruction Types 13.4.2 Read-Modify-Write Instructions These instructions read a memory location or a register, modify its contents, and write the modified value back to the memory location or to the register. NOTE: Do not use read-modify-write operations on write-only registers. Table 13-2. Read-Modify-Write Instructions Instruction Mnemonic ASL ASR BCLR(1) BSET(1) CLR COM DEC INC LSL LSR NEG ROL ROR TST(2) Freescale Semiconductor, Inc... Arithmetic Shift Left (Same as LSL) Arithmetic Shift Right Bit Clear Bit Set Clear Register Complement (One's Complement) Decrement Increment Logical Shift Left (Same as ASL) Logical Shift Right Negate (Two's Complement) Rotate Left through Carry Bit Rotate Right through Carry Bit Test for Negative or Zero 1. Unlike other read-modify-write instructions, BCLR and BSET use only direct addressing. 2. TST is an exception to the read-modify-write sequence because it does not write a replacement value. MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 13.4.3 Jump/Branch Instructions Jump instructions allow the CPU to interrupt the normal sequence of the program counter. The unconditional jump instruction (JMP) and the jump-to-subroutine instruction (JSR) have no register operand. Branch instructions allow the CPU to interrupt the normal sequence of the program counter when a test condition is met. If the test condition is not met, the branch is not performed. The BRCLR and BRSET instructions cause a branch based on the state of any readable bit in the first 256 memory locations. These 3-byte instructions use a combination of direct addressing and relative addressing. The direct address of the byte to be tested is in the byte following the opcode. The third byte is the signed offset byte. The CPU finds the effective branch destination by adding the third byte to the program counter if the specified bit tests true. The bit to be tested and its condition (set or clear) is part of the opcode. The span of branching is from -128 to +127 from the address of the next location after the branch instruction. The CPU also transfers the tested bit to the carry/borrow bit of the condition code register. NON-DISCLOSURE General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Instruction Set Instruction Types Table 13-3. Jump and Branch Instructions Instruction Branch if Carry Bit Clear Branch if Carry Bit Set Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Mnemonic BCC BCS BEQ BHCC BHCS BHI BHS BIH BIL BLO BLS BMC BMI BMS BNE BPL Freescale Semiconductor, Inc... Branch if Higher or Same Branch if IRQ Pin High Branch if IRQ Pin Low Branch if Lower Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always Branch if Bit Clear Branch Never Branch if Bit Set Branch to Subroutine Unconditional Jump Jump to Subroutine BRCLR BRN BRSET BSR JMP JSR MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE BRA AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 13.4.4 Bit Manipulation Instructions The CPU can set or clear any writable bit in the first 256 bytes of memory, which includes I/O registers and on-chip RAM locations. The CPU can also test and branch based on the state of any bit in any of the first 256 memory locations. Table 13-4. Bit Manipulation Instructions Instruction Mnemonic BCLR BRCLR BRSET BSET AGREEMENT Freescale Semiconductor, Inc... Bit Clear Branch if Bit Clear Branch if Bit Set Bit Set NON-DISCLOSURE General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Instruction Set Instruction Types 13.4.5 Control Instructions These instructions act on CPU registers and control CPU operation during program execution. Table 13-5. Control Instructions Instruction Clear Carry Bit Clear Interrupt Mask Mnemonic CLC CLI NOP RSP RTI RTS SEC SEI STOP SWI TAX TXA WAIT Freescale Semiconductor, Inc... No Operation Reset Stack Pointer Return from Interrupt Return from Subroutine Set Carry Bit Set Interrupt Mask Stop Oscillator and Enable IRQ Pin Software Interrupt Transfer Accumulator to Index Register Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Instruction Set REQUIRED 13.5 Instruction Set Summary Table 13-6. Instruction Set Summary Opcode Source Form ADC #opr ADC opr ADC opr ADC opr,X ADC opr,X ADC ,X ADD #opr ADD opr ADD opr ADD opr,X ADD opr,X ADD ,X AND #opr AND opr AND opr AND opr,X AND opr,X AND ,X ASL opr ASLA ASLX ASL opr,X ASL ,X ASR opr ASRA ASRX ASR opr,X ASR ,X BCC rel Operation Description H I NZC Add with Carry A (A) + (M) + (C) -- Freescale Semiconductor, Inc... AGREEMENT IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX REL ii A9 2 B9 dd 3 C9 hh ll 4 D9 ee ff 5 E9 ff 4 F9 3 AB ii 2 BB dd 3 CB hh ll 4 DB ee ff 5 EB ff 4 FB 3 ii A4 2 B4 dd 3 C4 hh ll 4 D4 ee ff 5 E4 ff 4 F4 3 38 48 58 68 78 37 47 57 67 77 24 11 13 15 17 19 1B 1D 1F 25 27 28 29 22 24 dd 5 3 3 6 5 5 3 3 6 5 3 5 5 5 5 5 5 5 5 3 3 3 3 3 3 Add without Carry A (A) + (M) -- Logical AND A (A) (M) ---- -- Arithmetic Shift Left (Same as LSL) C b7 b0 0 ---- NON-DISCLOSURE ff dd Arithmetic Shift Right b7 b0 C ---- ff rr dd dd dd dd dd dd dd dd rr rr rr rr rr rr Branch if Carry Bit Clear PC (PC) + 2 + rel ? C = 0 ---------- BCLR n opr Clear Bit n Mn 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- ---------- ---------- ---------- ---------- ---------- REL REL REL REL REL REL BCS rel BEQ rel BHCC rel BHCS rel BHI rel BHS rel Branch if Carry Bit Set (Same as BLO) Branch if Equal Branch if Half-Carry Bit Clear Branch if Half-Carry Bit Set Branch if Higher Branch if Higher or Same PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? Z = 1 PC (PC) + 2 + rel ? H = 0 PC (PC) + 2 + rel ? H = 1 PC (PC) + 2 + rel ? C Z = 0 PC (PC) + 2 + rel ? C = 0 General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Cycles Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. Instruction Set Instruction Set Summary Table 13-6. Instruction Set Summary (Continued) Opcode Source Form BIH rel BIL rel BIT #opr BIT opr BIT opr BIT opr,X BIT opr,X BIT ,X BLO rel BLS rel BMC rel BMI rel BMS rel BNE rel BPL rel BRA rel Operation Branch if IRQ Pin High Branch if IRQ Pin Low Description PC (PC) + 2 + rel ? IRQ = 1 PC (PC) + 2 + rel ? IRQ = 0 H I NZC ---------- ---------- REL REL IMM DIR EXT IX2 IX1 IX REL REL REL REL REL REL REL REL 2F 2E A5 B5 C5 D5 E5 F5 25 23 2C 2B 2D 26 2A 20 01 03 05 07 09 0B 0D 0F 21 00 02 04 06 08 0A 0C 0E 10 12 14 16 18 1A 1C 1E rr rr ii dd hh ll ee ff ff rr rr rr rr rr rr rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd rr dd dd dd dd dd dd dd dd Bit Test Accumulator with Memory Byte (A) (M) ---- -- Freescale Semiconductor, Inc... Cycles 3 3 2 3 4 5 4 3 3 3 3 3 3 3 3 3 5 5 5 5 5 5 5 5 3 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 5 6 2 2 Effect on CCR Branch if Lower (Same as BCS) Branch if Lower or Same Branch if Interrupt Mask Clear Branch if Minus Branch if Interrupt Mask Set Branch if Not Equal Branch if Plus Branch Always PC (PC) + 2 + rel ? C = 1 PC (PC) + 2 + rel ? C Z = 1 PC (PC) + 2 + rel ? I = 0 PC (PC) + 2 + rel ? N = 1 PC (PC) + 2 + rel ? I = 1 PC (PC) + 2 + rel ? Z = 0 PC (PC) + 2 + rel ? N = 0 PC (PC) + 2 + rel ? 1 = 1 ---------- ---------- ---------- ---------- ---------- ---------- ---------- ---------- BRCLR n opr rel Branch if Bit n Clear PC (PC) + 2 + rel ? Mn = 0 DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) ---------- REL BRN rel Branch Never PC (PC) + 2 + rel ? 1 = 0 BRSET n opr rel Branch if Bit n Set PC (PC) + 2 + rel ? Mn = 1 DIR (b0) DIR (b1) DIR (b2) DIR (b3) -------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) DIR (b0) DIR (b1) DIR (b2) DIR (b3) ---------- DIR (b4) DIR (b5) DIR (b6) DIR (b7) BSET n opr Set Bit n Mn 1 BSR rel Branch to Subroutine PC (PC) + 2; push (PCL) SP (SP) - 1; push (PCH) SP (SP) - 1 PC (PC) + rel C0 I0 ---------- REL AD rr CLC CLI Clear Carry Bit Clear Interrupt Mask -------- 0 -- 0 ------ INH INH 98 9A MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Operand Address Mode Freescale Semiconductor, Inc. Instruction Set REQUIRED Table 13-6. Instruction Set Summary (Continued) Opcode Source Form CLR opr CLRA CLRX CLR opr,X CLR ,X CMP #opr CMP opr CMP opr CMP opr,X CMP opr,X CMP ,X COM opr COMA COMX COM opr,X COM ,X CPX #opr CPX opr CPX opr CPX opr,X CPX opr,X CPX ,X DEC opr DECA DECX DEC opr,X DEC ,X EOR #opr EOR opr EOR opr EOR opr,X EOR opr,X EOR ,X INC opr INCA INCX INC opr,X INC ,X JMP opr JMP opr JMP opr,X JMP opr,X JMP ,X Operation Description M $00 A $00 X $00 M $00 M $00 H I NZC Clear Byte ---- 0 1 -- DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR EXT IX2 IX1 IX 3F 4F 5F 6F 7F dd ff Freescale Semiconductor, Inc... AGREEMENT Compare Accumulator with Memory Byte (A) - (M) ---- ii A1 2 B1 dd 3 C1 hh ll 4 D1 ee ff 5 E1 ff 4 F1 3 33 43 53 63 73 dd 5 3 3 6 5 Complement Byte (One's Complement) M (M) = $FF - (M) A (A) = $FF - (A) X (X) = $FF - (X) M (M) = $FF - (M) M (M) = $FF - (M) ---- 1 ff Compare Index Register with Memory Byte (X) - (M) ---- ii A3 2 B3 dd 3 C3 hh ll 4 D3 ee ff 5 E3 ff 4 F3 3 3A 4A 5A 6A 7A dd 5 3 3 6 5 NON-DISCLOSURE Decrement Byte M (M) - 1 A (A) - 1 X (X) - 1 M (M) - 1 M (M) - 1 ---- -- ff EXCLUSIVE OR Accumulator with Memory Byte A (A) (M) ---- -- ii A8 2 B8 dd 3 C8 hh ll 4 D8 ee ff 5 E8 ff 4 F8 3 3C 4C 5C 6C 7C dd 5 3 3 6 5 Increment Byte M (M) + 1 A (A) + 1 X (X) + 1 M (M) + 1 M (M) + 1 ---- -- ff Unconditional Jump PC Jump Address ---------- BC dd 2 CC hh ll 3 DC ee ff 4 EC ff 3 FC 2 General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Cycles 5 3 3 6 5 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. Instruction Set Instruction Set Summary Table 13-6. Instruction Set Summary (Continued) Opcode Source Form JSR opr JSR opr JSR opr,X JSR opr,X JSR ,X LDA #opr LDA opr LDA opr LDA opr,X LDA opr,X LDA ,X LDX #opr LDX opr LDX opr LDX opr,X LDX opr,X LDX ,X LSL opr LSLA LSLX LSL opr,X LSL ,X LSR opr LSRA LSRX LSR opr,X LSR ,X MUL NEG opr NEGA NEGX NEG opr,X NEG ,X NOP ORA #opr ORA opr ORA opr ORA opr,X ORA opr,X ORA ,X ROL opr ROLA ROLX ROL opr,X ROL ,X Operation Description H I NZC PC (PC) + n (n = 1, 2, or 3) Push (PCL); SP (SP) - 1 Push (PCH); SP (SP) - 1 PC Effective Address Jump to Subroutine ---------- DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX DIR INH INH IX1 IX INH DIR INH INH IX1 IX INH IMM DIR EXT IX2 IX1 IX DIR INH INH IX1 IX BD dd 5 CD hh ll 6 DD ee ff 7 ED ff 6 FD 5 ii A6 2 B6 dd 3 C6 hh ll 4 D6 ee ff 5 E6 ff 4 F6 3 AE ii 2 BE dd 3 CE hh ll 4 DE ee ff 5 EE ff 4 FE 3 38 48 58 68 78 34 44 54 64 74 42 30 40 50 60 70 9D AA BA CA DA EA FA 39 49 59 69 79 ii dd hh ll ee ff ff dd dd dd 5 3 3 6 5 5 3 3 6 5 11 5 3 3 6 5 2 2 3 4 5 4 3 5 3 3 6 5 Freescale Semiconductor, Inc... Load Index Register with Memory Byte X (M) ---- -- Logical Shift Left (Same as ASL) C b7 b0 0 ---- ff dd Logical Shift Right 0 b7 b0 C ---- 0 Unsigned Multiply X : A (X) x (A) M -(M) = $00 - (M) A -(A) = $00 - (A) X -(X) = $00 - (X) M -(M) = $00 - (M) M -(M) = $00 - (M) 0 ------ 0 Negate Byte (Two's Complement) ---- ff No Operation ---------- Logical OR Accumulator with Memory A (A) (M) ---- -- Rotate Byte Left through Carry Bit C b7 b0 ---- ff MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE ff AGREEMENT Load Accumulator with Memory Byte A (M) ---- -- Cycles Effect on CCR REQUIRED Operand Address Mode Freescale Semiconductor, Inc. Instruction Set REQUIRED Table 13-6. Instruction Set Summary (Continued) Opcode Source Form ROR opr RORA RORX ROR opr,X ROR ,X RSP Operation Description H I NZC Rotate Byte Right through Carry Bit b7 b0 C ---- DIR INH INH IX1 IX INH 36 46 56 66 76 9C dd ff Reset Stack Pointer SP $00FF SP (SP) + 1; Pull (CCR) SP (SP) + 1; Pull (A) SP (SP) + 1; Pull (X) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) SP (SP) + 1; Pull (PCH) SP (SP) + 1; Pull (PCL) ---------- Freescale Semiconductor, Inc... AGREEMENT RTI Return from Interrupt INH 80 RTS SBC #opr SBC opr SBC opr SBC opr,X SBC opr,X SBC ,X SEC SEI STA opr STA opr STA opr,X STA opr,X STA ,X STOP STX opr STX opr STX opr,X STX opr,X STX ,X SUB #opr SUB opr SUB opr SUB opr,X SUB opr,X SUB ,X Return from Subroutine ---------- INH IMM DIR EXT IX2 IX1 IX INH INH DIR EXT IX2 IX1 IX INH DIR EXT IX2 IX1 IX IMM DIR EXT IX2 IX1 IX 81 Subtract Memory Byte and Carry Bit from Accumulator A (A) - (M) - (C) ---- ii A2 2 B2 dd 3 C2 hh ll 4 D2 ee ff 5 E2 ff 4 F2 3 99 9B B7 C7 D7 E7 F7 8E BF CF DF EF FF dd hh ll ee ff ff dd hh ll ee ff ff 2 2 4 5 6 5 4 2 4 5 6 5 4 Set Carry Bit Set Interrupt Mask C1 I1 -------- 1 -- 1 ------ NON-DISCLOSURE Store Accumulator in Memory M (A) ---- -- Stop Oscillator and Enable IRQ Pin -- 0 ------ Store Index Register In Memory M (X) ---- -- Subtract Memory Byte from Accumulator A (A) - (M) ---- ii A0 2 B0 dd 3 C0 hh ll 4 D0 ee ff 5 E0 ff 4 F0 3 SWI Software Interrupt PC (PC) + 1; Push (PCL) SP (SP) - 1; Push (PCH) SP (SP) - 1; Push (X) SP (SP) - 1; Push (A) -- 1 ------ SP (SP) - 1; Push (CCR) SP (SP) - 1; I 1 PCH Interrupt Vector High Byte PCL Interrupt Vector Low Byte X (A) ---------- INH 83 10 TAX Transfer Accumulator to Index Register INH 97 General Release Specification Instruction Set For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Cycles 5 3 3 6 5 2 9 6 2 Effect on CCR Operand Address Mode Freescale Semiconductor, Inc. Instruction Set Instruction Set Summary Table 13-6. Instruction Set Summary (Continued) Opcode Source Form TST opr TSTA TSTX TST opr,X TST ,X TXA Operation Description H I NZC Test Memory Byte for Negative or Zero (M) - $00 ---- -- DIR INH INH IX1 IX INH INH 3D 4D 5D 6D 7D 9F 8F dd ff Transfer Index Register to Accumulator Stop CPU Clock and Enable Interrupts Accumulator Carry/borrow flag Condition code register Direct address of operand Direct address of operand and relative offset of branch instruction Direct addressing mode High and low bytes of offset in indexed, 16-bit offset addressing Extended addressing mode Offset byte in indexed, 8-bit offset addressing Half-carry flag High and low bytes of operand address in extended addressing Interrupt mask Immediate operand byte Immediate addressing mode Inherent addressing mode Indexed, no offset addressing mode Indexed, 8-bit offset addressing mode Indexed, 16-bit offset addressing mode Memory location Negative flag Any bit A (X) ---------- -- 0------ Freescale Semiconductor, Inc... WAIT A C CCR dd dd rr DIR ee ff EXT ff H hh ll I ii IMM INH IX IX1 IX2 M N n 2 Cycles 4 3 3 5 4 2 Effect on CCR MC68HC05E5 -- Rev. 1.0 Instruction Set For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE opr PC PCH PCL REL rel rr SP X Z # () -( ) ? : -- Operand (one or two bytes) Program counter Program counter high byte Program counter low byte Relative addressing mode Relative program counter offset byte Relative program counter offset byte Stack pointer Index register Zero flag Immediate value Logical AND Logical OR Logical EXCLUSIVE OR Contents of Negation (two's complement) Loaded with If Concatenated with Set or cleared Not affected AGREEMENT REQUIRED Operand Address Mode N O N - D I S C LFreescale Semiconductor, IN T OSURE A G R E E M E nc... R E Q U I R E D Table 13-7. Opcode Map Branch Register/Memory IMM IX F 3 SUB IX 3 CMP IX 3 SBC IX 3 CPX IX 3 AND IX 3 BIT IX 3 LDA IX 4 STA 2 IX 3 EOR IX 3 ADC IX 3 ORA 1 1 1 1 IX 3 ADD IX 2 JMP 2 IX 5 JSR IX 3 LDX IX 4 STX 2 MSB LSB IX MSB LSB Bit Manipulation Control IX INH INH IX1 E 9 A B C D IX2 8 EXT 7 DIR REL DIR INH INH 5 6 4 3 2 IX1 Read-Modify-Write DIR DIR MSB LSB 2 2 2 10 SWI INH 2 2 2 2 1 1 1 0 1 Instruction Set 0 1 2 3 4 5 6 7 8 9 A B C D E F 0 General Release Specification 9 RTI INH 6 RTS INH 2 SUB IMM 2 2 CMP IMM 2 2 SBC IMM 2 2 CPX IMM 2 2 AND IMM 2 2 BIT IMM 2 2 LDA IMM 2 2 EOR IMM 2 2 ADC IMM 2 2 ORA IMM 2 2 ADD IMM 2 2 TAX INH 2 CLC INH 2 2 SEC INH 2 2 CLI INH 2 2 SEI INH 2 2 RSP INH 2 NOP INH 2 6 BSR REL 2 2 LDX 2 IMM 2 2 STOP INH 2 2 TXA WAIT INH 1 INH 3 SUB DIR 3 3 CMP DIR 3 3 SBC DIR 3 3 CPX DIR 3 3 AND DIR 3 3 BIT DIR 3 3 LDA DIR 3 4 STA DIR 3 3 EOR DIR 3 3 ADC DIR 3 3 ORA DIR 3 3 ADD DIR 3 2 JMP DIR 3 5 JSR DIR 3 3 LDX DIR 3 4 STX DIR 3 4 SUB EXT 3 4 CMP EXT 3 4 SBC EXT 3 4 CPX EXT 3 4 AND EXT 3 4 BIT EXT 3 4 LDA EXT 3 5 STA EXT 3 4 EOR EXT 3 4 ADC EXT 3 4 ORA EXT 3 4 ADD EXT 3 3 JMP EXT 3 6 JSR EXT 3 4 LDX EXT 3 5 STX EXT 3 5 SUB IX2 2 5 CMP IX2 2 5 SBC IX2 2 5 CPX IX2 2 5 AND IX2 2 5 BIT IX2 2 5 LDA IX2 2 6 STA IX2 2 5 EOR IX2 2 5 ADC IX2 2 5 ORA IX2 2 5 ADD IX2 2 4 JMP IX2 2 7 JSR IX2 2 5 LDX IX2 2 6 STX IX2 2 4 SUB IX1 1 4 CMP IX1 1 4 SBC IX1 1 4 CPX IX1 1 4 AND IX1 1 4 BIT IX1 1 4 LDA IX1 1 5 STA IX1 1 4 EOR IX1 1 4 ADC IX1 1 4 ORA IX1 1 4 ADD IX1 1 3 JMP IX1 1 6 JSR IX1 1 4 LDX IX1 1 5 STX IX1 1 1 2 3 4 5 6 7 8 9 A B Freescale Semiconductor, Inc. Instruction Set For More Information On This Product, Go to: www.freescale.com 0 LSB of Opcode in Hexadecimal REL = Relative IX = Indexed, No Offset IX1 = Indexed, 8-Bit Offset IX2 = Indexed, 16-Bit Offset C D E F 5 5 3 5 3 3 6 5 BRSET0 BRA BSET0 NEG NEGA NEGX NEG NEG 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 BRCLR0 BRN BCLR0 3 1 DIR 2 DIR 2 REL 5 11 5 3 BRSET1 MUL BHI BSET1 3 1 DIR 2 INH DIR 2 REL 5 5 3 5 3 3 6 5 BRCLR1 BLS BCLR1 COM COMA COMX COM COM 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 5 5 3 5 3 3 6 5 BRSET2 BCC BSET2 LSR LSRA LSRX LSR LSR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR2 BCLR2 BCS/BLO 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET3 BNE BSET3 ROR RORA RORX ROR ROR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR3 BEQ BCLR3 ASR ASRA ASRX ASR ASR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET4 BHCC BSET4 ASL/LSL ASLA/LSLA ASLX/LSLX ASL/LSL ASL/LSL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRCLR4 BHCS BCLR4 ROL ROLA ROLX ROL ROL 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 5 3 3 6 5 BRSET5 BPL BSET5 DEC DECA DECX DEC DEC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRCLR5 BMI BCLR5 3 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRSET6 BMC BSET6 INC INCA INCX INC INC 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 4 3 3 5 4 BRCLR6 BMS BCLR6 TST TSTA TSTX TST TST 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 5 5 3 BRSET7 BIL BSET7 3 1 DIR 2 DIR 2 REL 5 5 3 5 3 3 6 5 BRCLR7 BIH BCLR7 CLR CLRA CLRX CLR CLR 3 DIR 2 DIR 2 REL 2 DIR 1 INH 1 INH 2 IX1 1 IX 1 MSB of Opcode in Hexadecimal MC68HC05E5 -- Rev. 1.0 INH = Inherent IMM = Immediate DIR = Direct EXT = Extended 0 5 Number of Cycles BRSET0 Opcode Mnemonic 3 DIR Number of Bytes/Addressing Mode Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 14. Electrical Specifications 14.1 Contents 14.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .123 Maximum Ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .124 Operating Temperature Range. . . . . . . . . . . . . . . . . . . . . . . .125 Thermal Characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . .125 DC Electrical Characteristics . . . . . . . . . . . . . . . . . . . . . . . . .126 Control Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .128 M-Bus Interface Input Signal Timing. . . . . . . . . . . . . . . . . . . .130 M-Bus Interface Output Signal Timing . . . . . . . . . . . . . . . . . .130 Freescale Semiconductor, Inc... 14.3 14.4 14.5 14.6 14.7 14.8 14.9 This section contains the electrical and timing specifications. MC68HC05E5 -- Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 14.2 Introduction AGREEMENT REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 14.3 Maximum Ratings Maximum ratings are the extreme limits to which the MCU can be exposed without permanently damaging it. The MCU contains circuitry to protect the inputs against damage from high static voltages; however, do not apply voltages higher than those shown in the table below. Keep VIN and VOUT within the range VSS (VIN or VOUT) VDD. Connect unused inputs to the appropriate voltage level, either VSS or VDD. Rating Supply Voltage Input Voltage Self-Check Mode (IRQ Pin Only) Current Drain Per Pin Excluding VDD and VSS Storage Temperature Range Symbol VDD VIN VIN I TSTG Value -0.3 to +7.0 VSS -0.3 to VDD +0.3 VSS -0.3 to 2 x VDD +0.3 25 -65 to +150 Unit V V V mA C Freescale Semiconductor, Inc... AGREEMENT NOTE: NON-DISCLOSURE This device is not guaranteed to operate properly at the maximum ratings. Refer to 14.6 DC Electrical Characteristics for guaranteed operating conditions. General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Electrical Specifications Operating Temperature Range 14.4 Operating Temperature Range Characteristic Operating Temperature Range MC68HC(7)05E5DW (Standard) MC68HC(7)05E5P Symbol TA Value TL to TH 0 to +70 0 to +70 Unit C 14.5 Thermal Characteristics Freescale Semiconductor, Inc... Thermal Resistance Plastic DIP SOIC I/O Pin Power Dissipation Power Dissipation(1) Constant(2) Average Junction Temperature Maximum Junction Temperature JA PI/O PD K TJ TJM 60 60 User Determined PD = (IDD x VDD) + PI/O = K/(TJ + 273 C) PD x (TA + 273 C) + PD2 x JA TA + (PD x JA) 125 C/W W W W/C C C MC68HC05E5 -- Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE NOTES: 1. Power dissipation is a function of temperature. 2. K is a constant unique to the device. K can be determined for a known TA and measured PD. With this value of K, PD and TJ can be determined for any value of TA. AGREEMENT Characteristic Symbol Value Unit REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 14.6 DC Electrical Characteristics Characteristic Output Voltage ILOAD = 10.0 A ILOAD = -10.0 A Output High Voltage (ILOAD -0.8 mA) PA0-PA7, PB0-PB7, PC0-PC3 Output Low Voltage (ILOAD = 1.6 mA) PA0-PA7, PB0-PB7, PC0-PC3 Input High Voltage PA0-PA7, PB0-PB7, PC0-PC3, IRQ, RESET, OSC1 Input Low Voltage PA0-PA7, PB0-PB7, PC0-PC3, IRQ, RESET, OSC1 XFC Wide Bandwidth Source Sink XFC Narrow Bandwidth Source Sink Supply Current (see Notes) Run (fosc = 32.768 kHz, fop = 16.384 kHz) (fosc = 4.2 MHz, fop = 2.1 MHz) Wait (fosc = 32.768 kHz, fop = 16.384 kHz) (fosc = 4.2 MHz, fop = 2.1 MHz) Stop (PLL Off) 25 oC I/O Ports Hi-Z Leakage Current PA0-PA7, PB0-PB7, PC0-PC3 Input Current RESET, IRQ, OSC1 Capacitance Ports as Input or Output RESET, IRQ Symbol VOL VOH VOH VOL VIH VIL IOH IOL IOH IOL Min -- VDD -0.1 VDD -0.8 -- 0.7 x VDD VSS -50 50 -1 1 Typ -- -- -- -- -- -- Max 0.1 -- -- 0.4 VDD 0.3 x VDD -- -- -- -- Unit V V V V V A Freescale Semiconductor, Inc... AGREEMENT -100 100 -2 2 A -- -- IDD -- -- -- IOZ IIN COUT CINT -- -- 120 2.5 50 0.7 10 -- -- 400 3.5 150 1 50 10 1 A mA A mA A A A pF NON-DISCLOSURE -- -- -- -- 12 8 NOTES: 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 0 C to +70 C, unless otherwise noted 2. Typical values at midpoint of voltage range, 25 C only 3. Wait IDD: Only timer and CPI systems active 4. Run (Operating) IDD, wait IDD: Measured using external square wave clock source; all inputs 0.2 V from rail; no dc loads; less than 50 pF on all outputs; CL = 20 pF on OSC2 5. Wait, stop IDD: All ports configured as inputs; VIL = 0.2; VIH = VDD -0.2 V 6. Stop IDD measured with OSC1 = VSS 7. Wait IDD affected linearly by the OSC2 capacitance General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Electrical Specifications DC Electrical Characteristics 3.5 3.0 SUPPLY CURRENT (mA) 2.5 2.0 1.5 1.0 VDD = 5.0 V TA = -0 C to 70 C RU NID D WAIT I DD Freescale Semiconductor, Inc... 0.5 0 0.016 0.277 0.537 0.798 1.058 1.319 1.579 1.840 2.100 OPERATING FREQUENCY (MHz) Figure 14-1. Maximum Supply Current versus Operating Frequency 2.5 VDD = 5.0 V TA = -0 C to 70 C 2.0 SUPPLY CURRENT (mA) RU NID D 1.0 I DD 0.5 WAIT 0 0.016 0.277 0.537 0.798 1.058 1.319 1.579 1.840 2.100 OPERATING FREQUENCY (MHz) Figure 14-2. Typical Supply Current versus Operating Frequency MC68HC05E5 -- Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE 1.5 AGREEMENT REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 14.7 Control Timing Characteristic Frequency of Operation Crystal Option External Clock Option Internal Operating Frequency Crystal (fOSC / 2) External Clock (fOSC / 2) Cycle Time Symbol fOSC Min -- dc -- dc 480 1.5 125 see Note 2 90 50 Max 32.768 4.2 16.384 2.1 -- -- -- -- -- -- Unit kHz MHz kHz MHz ns tCYC ns tCYC ns ms fOP tCYC tRL tILIH tILIL tOH, tOL tPLLS Freescale Semiconductor, Inc... AGREEMENT RESET Pulse Width Interrupt Pulse Width Low (Edge-Triggered) Interrupt Pulse Period OSC1 Pulse Width PLL Startup Stabilization Time NOTES: 1. VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = 0 oC to +70 oC, unless otherwise noted 2. The minimum period, tILIL, should not be less than the number of cycle times it takes to execute the interrupt service routine plus 19 tcyc. NON-DISCLOSURE IRQ tILIH tILIH IRQ1 . . . IRQn tILIH NORMALLY USED WITH WIRE-ORed CONNECTION IRQ (MCU) Figure 14-3. External Interrupt Mode Diagram General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc... tVDDR MC68HC05E5 -- Rev. 1.0 4064 tCYC tCYC 1FFE 1FFF NEW PC NEW PC 1FFE 1FFE 1FFE 1FFE 1FFF NEW PC NEW PC NEW PCH NEW PCL tRL 3 OP CODE PCH PCL OP CODE VDD VDD THRESHOLD (1 TO 2 V TYPICAL) OSC12 INTERNAL PROCESSOR CLOCK1 INTERNAL ADDRESS BUS1 INTERNAL DATA BUS1 Freescale Semiconductor, Inc. Electrical Specifications For More Information On This Product, Go to: www.freescale.com RESET NOTES: 1. Internal timing signal and bus information are not available externally. 2. OSC1 line is not meant to represent frequency. It is only used to represent time. 3. The next rising edge of the internal processor clock following the rising edge of RESET initiates the reset sequence. General Release Specification Electrical Specifications Control Timing Figure 14-4. Power-On Reset and RESET NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED 14.8 M-Bus Interface Input Signal Timing Characteristic Start Condition Hold Time Clock Low Period Clock High Period SDA/SCL Rise Time SDA/SCL Fall Time Symbol tHD.STA tLOW tHIGH tR tF tSU.DAT tHD.DAT tSU.STA tSU.STO Min 2 4.7 4 -- -- 250 0 2 2 Max -- -- -- 1.0 300 -- -- -- -- Unit tcyc tcyc tcyc ms ns ns tcyc tcyc tcyc AGREEMENT Freescale Semiconductor, Inc... Data Setup Time Data Hold Time Start Condition Setup Time (For Repeated Start Condition Only) Stop Condition Setup Time NOTE: VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 oC to +85 oC, unless otherwise noted 14.9 M-Bus Interface Output Signal Timing Characteristic Start Condition Hold Time Clock Low Period Clock High Period SDA/SCL Rise Time SDA/SCL Fall Time Data Setup Time Data Hold Time Start Condition Setup Time (For Repeated Start Condition Only) Stop Condition Setup Time Symbol tHD.STA tLOW tHIGH tR tF tSU.DAT tHD.DAT tSU.STA tSU.STO Min 12 11 11 -- -- tLow-tcyc 0 10 12 Max -- -- -- 1.0 300 -- -- -- -- Unit tcyc tcyc tcyc ms ns ns tcyc tcyc tcyc NON-DISCLOSURE NOTE: VDD = 5.0 Vdc 10%, VSS = 0 Vdc, TA = -40 oC to +85 oC, unless otherwise noted General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Electrical Specifications M-Bus Interface Output Signal Timing SDA SCL tHD.STA tLOW tHIGH tSU.DAT tHD.DAT tSU.STO Freescale Semiconductor, Inc... MC68HC05E5 -- Rev. 1.0 Electrical Specifications For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT Figure 14-5. M-Bus Interface Timing REQUIRED Freescale Semiconductor, Inc. Electrical Specifications REQUIRED NON-DISCLOSURE General Release Specification Electrical Specifications For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc... AGREEMENT MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 15. Mechanical Data 15.1 Contents 15.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .133 28-Pin Plastic Dual-in-Line Package (Case 710-02) . . . . . . .133 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) . . . . . . . . . . . . . . . . . . . .134 Freescale Semiconductor, Inc... 15.3 15.4 15.2 Introduction This section describes the dimensions of the plastic dual in-line package (PDIP) and small outline integrated circuit (SOIC) MCU packages. 15.3 28-Pin Plastic Dual-in-Line Package (Case 710-02) NON-DISCLOSURE 28 15 B 1 14 NOTES: 1. POSITIONAL TOLERANCE OF LEADS (D), SHALL BE WITHIN 0.25mm (0.010) AT MAXIMUM MATERIAL CONDITION, IN RELATION TO SEATING PLANE AND EACH OTHER. 2. DIMENSION L TO CENTER OF LEADS WHEN FORMED PARALLEL. 3. DIMENSION B DOES NOT INCLUDE MOLD FLASH. DIM A B C D F G H J K L M N MILLIMETERS MIN MAX 36.45 37.21 13.72 14.22 3.94 5.08 0.36 0.56 1.02 1.52 2.54 BSC 1.65 2.16 0.20 0.38 2.92 3.43 15.24 BSC 0 15 0.51 1.02 INCHES MIN MAX 1.435 1.465 0.540 0.560 0.155 0.200 0.014 0.022 0.040 0.060 0.100 BSC 0.065 0.085 0.008 0.015 0.115 0.135 0.600 BSC 0 15 0.020 0.040 A N C L H G F D K SEATING PLANE M J MC68HC05E5 -- Rev. 1.0 Mechanical Data For More Information On This Product, Go to: www.freescale.com General Release Specification AGREEMENT REQUIRED Freescale Semiconductor, Inc. Mechanical Data REQUIRED 15.4 28-Pin Small Outline Integrated Circuit Package (Case 751F-04) -A28 15 14X -B1 14 P 0.010 (0.25) M B M 28X D 0.010 (0.25) M T A S B S M R X 45 NOTES: 1. DIMENSIONING AND TOLERANCING PER ANSI Y14.5M, 1982. 2. CONTROLLING DIMENSION: MILLIMETER. 3. DIMENSION A AND B DO NOT INCLUDE MOLD PROTRUSION. 4. MAXIMUM MOLD PROTRUSION 0.15 (0.006) PER SIDE. 5. DIMENSION D DOES NOT INCLUDE DAMBAR PROTRUSION. ALLOWABLE DAMBAR PROTRUSION SHALL BE 0.13 (0.005) TOTAL IN EXCESS OF D DIMENSION AT MAXIMUM MATERIAL CONDITION. DIM A B C D F G J K M P R MILLIMETERS MIN MAX 17.80 18.05 7.60 7.40 2.65 2.35 0.49 0.35 0.90 0.41 1.27 BSC 0.32 0.23 0.29 0.13 8 0 10.05 10.55 0.75 0.25 INCHES MIN MAX 0.701 0.711 0.292 0.299 0.093 0.104 0.014 0.019 0.016 0.035 0.050 BSC 0.009 0.013 0.005 0.011 8 0 0.395 0.415 0.010 0.029 Freescale Semiconductor, Inc... AGREEMENT -T26X C G K -TSEATING PLANE F J NON-DISCLOSURE General Release Specification Mechanical Data For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. General Release Specification -- MC68HC05E5 Section 16. Ordering Information 16.1 Contents 16.2 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 MCU Ordering Forms . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .135 Application Program Media. . . . . . . . . . . . . . . . . . . . . . . . . . .136 ROM Program Verification . . . . . . . . . . . . . . . . . . . . . . . . . . .137 ROM Verification Units (RVUs). . . . . . . . . . . . . . . . . . . . . . . .138 MC Order Numbers . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .138 Freescale Semiconductor, Inc... 16.3 16.4 16.5 16.6 16.7 16.2 Introduction This section contains instructions for ordering custom-masked ROM MCUs. 16.3 MCU Ordering Forms To initiate an order for a ROM-based MCU, first obtain the current ordering form for the MCU from a Motorola representative. Submit the following items when ordering MCUs: * * * A current MCU ordering form that is completely filled out (Contact your Motorola sales office for assistance.) A copy of the customer specification if the customer specification deviates from the Motorola specification for the MCU Customer's application program on one of the media listed in 16.4 Application Program Media MC68HC05E5 -- Rev. 1.0 Ordering Information For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Ordering Information REQUIRED The current MCU ordering form is also available through the Motorola Freeware Bulletin Board Service (BBS). The telephone number is (512) 891-FREE. After making the connection, type bbs in lowercase letters. Then press the return key to start the BBS software. 16.4 Application Program Media Please deliver the application program to Motorola in one of the following media: * * * Macintosh(R)1 3 1/2-inch diskette (double-sided 800 K or double-sided high-density 1.4 M) MS-DOS(R)2 or PC-DOSTM3 3 1/2-inch diskette (double-sided 720 K or double-sided high-density 1.44 M) MS-DOS(R) or PC-DOSTM 5 1/4-inch diskette (double-sided double-density 360 K or double-sided high-density 1.2 M) Freescale Semiconductor, Inc... AGREEMENT Use positive logic for data and addresses. When submitting the application program on a diskette, clearly label the diskette with the following information: * * * * * * * Customer name Customer part number Project or product name File name of object code Date Name of operating system that formatted diskette Formatted capacity of diskette NON-DISCLOSURE On diskettes, the application program must be in Motorola's S-record format (S1 and S9 records), a character-based object file format generated by M6805 cross assemblers and linkers. 1. Macintosh is a registered trademark of Apple Computer, Inc. 2. MS-DOS is a registered trademark of Microsoft Corporation. 3. PC-DOS is a trademark of International Business Machines Corporation. General Release Specification Ordering Information For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Ordering Information ROM Program Verification NOTE: Begin the application program at the first user ROM location. Program addresses must correspond exactly to the available on-chip user ROM addresses as shown in the memory map. Write $00 in all nonuser ROM locations or leave all nonuser ROM locations blank. Refer to the current MCU ordering form for additional requirements. Motorola may request pattern re-submission if nonuser areas contain any nonzero code. If the memory map has two user ROM areas with the same addresses, then write the two areas in separate files on the diskette. Label the diskette with both filenames. Freescale Semiconductor, Inc... In addition to the object code, a file containing the source code can be included. Motorola keeps this code confidential and uses it only to expedite ROM pattern generation in case of any difficulty with the object code. Label the diskette with the filename of the source code. 16.5 ROM Program Verification The primary use for the on-chip ROM is to hold the customer's application program. The customer develops and debugs the application program and then submits the MCU order along with the application program. Motorola inputs the customer's application program code into a computer program that generates a listing verify file. The listing verify file represents the memory map of the MCU. The listing verify file contains the user ROM code and may also contain nonuser ROM code, such as self-check code. Motorola sends the customer a computer printout of the listing verify file along with a listing verify form. To aid the customer in checking the listing verify file, Motorola will program the listing verify file into customer-supplied blank preformatted Macintosh or DOS disks. All original pattern media are filed for contractual purposes and are not returned. Check the listing verify file thoroughly, then complete and sign the listing verify form and return the listing verify form to Motorola. The signed listing verify form constitutes the contractual agreement for the creation of the custom mask. MC68HC05E5 -- Rev. 1.0 Ordering Information For More Information On This Product, Go to: www.freescale.com General Release Specification NON-DISCLOSURE AGREEMENT REQUIRED Freescale Semiconductor, Inc. Ordering Information REQUIRED 16.6 ROM Verification Units (RVUs) After receiving the signed listing verify form, Motorola manufactures a custom photographic mask. The mask contains the customer's application program and is used to process silicon wafers. The application program cannot be changed after the manufacture of the mask begins. Motorola then produces 10 MCUs, called RVUs, and sends the RVUs to the customer. RVUs are usually packaged in unmarked ceramic and tested to 5 Vdc at room temperature. RVUs are not tested to environmental extremes because their sole purpose is to demonstrate that the customer's user ROM pattern was properly implemented. The 10 RVUs are free of charge with the minimum order quantity. These units are not to be used for qualification or production. RVUs are not guaranteed by Motorola Quality Assurance. Freescale Semiconductor, Inc... AGREEMENT 16.7 MC Order Numbers Table 16-1 shows the MC order numbers for the available package types. Table 16-1. MC Order Numbers Package Type 28-Pin Plastic Dual In-Line Package (PDIP) 28-Pin Small Outline Integrated Circuit Package (SOIC) Operating Temperature Range 0 C to 70C 0 C to 70C MC Order Number MC68HC05E5P MC68HC05E5DW NON-DISCLOSURE General Release Specification Ordering Information For More Information On This Product, Go to: www.freescale.com MC68HC05E5 -- Rev. 1.0 Freescale Semiconductor, Inc. Freescale Semiconductor, Inc... For More Information On This Product, Go to: www.freescale.com Freescale Semiconductor, Inc. Home Page: www.freescale.com email: support@freescale.com USA/Europe or Locations Not Listed: Freescale Semiconductor Technical Information Center, CH370 1300 N. Alma School Road Chandler, Arizona 85224 (800) 521-6274 480-768-2130 support@freescale.com Europe, Middle East, and Africa: Freescale Halbleiter Deutschland GmbH Technical Information Center Schatzbogen 7 81829 Muenchen, Germany +44 1296 380 456 (English) +46 8 52200080 (English) +49 89 92103 559 (German) +33 1 69 35 48 48 (French) support@freescale.com Japan: Freescale Semiconductor Japan Ltd. Headquarters ARCO Tower 15F 1-8-1, Shimo-Meguro, Meguro-ku Tokyo 153-0064, Japan 0120 191014 +81 2666 8080 support.japan@freescale.com Asia/Pacific: Freescale Semiconductor Hong Kong Ltd. Technical Information Center 2 Dai King Street Tai Po Industrial Estate, Tai Po, N.T., Hong Kong +800 2666 8080 support.asia@freescale.com For Literature Requests Only: Freescale Semiconductor Literature Distribution Center P.O. Box 5405 Denver, Colorado 80217 (800) 441-2447 303-675-2140 Fax: 303-675-2150 LDCForFreescaleSemiconductor @hibbertgroup.com RoHS-compliant and/or Pb- free versions of Freescale products have the functionality and electrical characteristics of their non-RoHS-compliant and/or non-Pb- free counterparts. For further information, see http://www.freescale.com or contact your Freescale sales representative. For information on Freescale.s Environmental Products program, go to http://www.freescale.com/epp. Freescale Semiconductor, Inc... Information in this document is provided solely to enable system and software implementers to use Freescale Semiconductor products. There are no express or implied copyright licenses granted hereunder to design or fabricate any integrated circuits or integrated circuits based on the information in this document. Freescale Semiconductor reserves the right to make changes without further notice to any products herein. Freescale Semiconductor makes no warranty, representation or guarantee regarding the suitability of its products for any particular purpose, nor does Freescale Semiconductor assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including without limitation consequential or incidental damages. "Typical" parameters which may be provided in Freescale Semiconductor data sheets and/or specifications can and do vary in different applications and actual performance may vary over time. All operating parameters, including "Typicals" must be validated for each customer application by customer's technical experts. Freescale Semiconductor does not convey any license under its patent rights nor the rights of others. Freescale Semiconductor products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the Freescale Semiconductor product could create a situation where personal injury or death may occur. Should Buyer purchase or use Freescale Semiconductor products for any such unintended or unauthorized application, Buyer shall indemnify and hold Freescale Semiconductor and its officers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, directly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that Freescale Semiconductor was negligent regarding the design or manufacture of the part. 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